1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu #include <sgi_ras.h> 9*91f16700Schasinglulu #include <sgi_sdei.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu struct sgi_ras_ev_map plat_ras_map[] = { 12*91f16700Schasinglulu /* Non Secure base RAM ECC CE interrupt */ 13*91f16700Schasinglulu {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, SGI_RAS_INTR_TYPE_SPI}, 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Non Secure base RAM ECC UE interrupt */ 16*91f16700Schasinglulu {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI}, 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* CPU 1-bit ECC CE error interrupt */ 19*91f16700Schasinglulu {SGI_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, SGI_RAS_INTR_TYPE_PPI} 20*91f16700Schasinglulu }; 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* RAS error record list definition, used by the common RAS framework. */ 23*91f16700Schasinglulu struct err_record_info plat_err_records[] = { 24*91f16700Schasinglulu /* Base element RAM Non-secure error record. */ 25*91f16700Schasinglulu ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL, 26*91f16700Schasinglulu &sgi_ras_sram_intr_handler, 0), 27*91f16700Schasinglulu ERR_RECORD_SYSREG_V1(0, 1, NULL, &sgi_ras_cpu_intr_handler, 0), 28*91f16700Schasinglulu }; 29*91f16700Schasinglulu 30*91f16700Schasinglulu /* RAS error interrupt list definition, used by the common RAS framework. */ 31*91f16700Schasinglulu struct ras_interrupt plat_ras_interrupts[] = { 32*91f16700Schasinglulu { 33*91f16700Schasinglulu .intr_number = PLAT_CORE_FAULT_IRQ, 34*91f16700Schasinglulu .err_record = &plat_err_records[1], 35*91f16700Schasinglulu }, { 36*91f16700Schasinglulu .intr_number = NS_RAM_ECC_CE_INT, 37*91f16700Schasinglulu .err_record = &plat_err_records[0], 38*91f16700Schasinglulu }, { 39*91f16700Schasinglulu .intr_number = NS_RAM_ECC_UE_INT, 40*91f16700Schasinglulu .err_record = &plat_err_records[0], 41*91f16700Schasinglulu }, 42*91f16700Schasinglulu }; 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* Registers the RAS error record list with common RAS framework. */ 45*91f16700Schasinglulu REGISTER_ERR_RECORD_INFO(plat_err_records); 46*91f16700Schasinglulu /* Registers the RAS error interrupt info list with common RAS framework. */ 47*91f16700Schasinglulu REGISTER_RAS_INTERRUPTS(plat_ras_interrupts); 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* Platform RAS handling config data definition */ 50*91f16700Schasinglulu struct plat_sgi_ras_config ras_config = { 51*91f16700Schasinglulu plat_ras_map, 52*91f16700Schasinglulu ARRAY_SIZE(plat_ras_map) 53*91f16700Schasinglulu }; 54