1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2020 - 2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu/dts-v1/; 8*91f16700Schasinglulu/ { 9*91f16700Schasinglulu /* compatible string */ 10*91f16700Schasinglulu compatible = "arm,rd-n2"; 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* 13*91f16700Schasinglulu * Place holder for system-id node with default values. The 14*91f16700Schasinglulu * value of platform-id and config-id will be set to the 15*91f16700Schasinglulu * correct values during the BL2 stage of boot. 16*91f16700Schasinglulu */ 17*91f16700Schasinglulu system-id { 18*91f16700Schasinglulu platform-id = <0x0>; 19*91f16700Schasinglulu config-id = <0x0>; 20*91f16700Schasinglulu multi-chip-mode = <0x0>; 21*91f16700Schasinglulu /* 22*91f16700Schasinglulu * First cell pair: Count of isolated CPUs in the list. 23*91f16700Schasinglulu * Rest of the cells: MPID list of the isolated CPUs. 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu isolated-cpu-list = <0x0 0x0 26*91f16700Schasinglulu 0x0 0x0 27*91f16700Schasinglulu 0x0 0x0 28*91f16700Schasinglulu 0x0 0x0 29*91f16700Schasinglulu 0x0 0x0 30*91f16700Schasinglulu 0x0 0x0 31*91f16700Schasinglulu 0x0 0x0 32*91f16700Schasinglulu 0x0 0x0 33*91f16700Schasinglulu 0x0 0x0 34*91f16700Schasinglulu 0x0 0x0 35*91f16700Schasinglulu 0x0 0x0 36*91f16700Schasinglulu 0x0 0x0 37*91f16700Schasinglulu 0x0 0x0 38*91f16700Schasinglulu 0x0 0x0 39*91f16700Schasinglulu 0x0 0x0 40*91f16700Schasinglulu 0x0 0x0 41*91f16700Schasinglulu 0x0 0x0>; 42*91f16700Schasinglulu }; 43*91f16700Schasinglulu}; 44