1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <sgi_dmc620_tzc_regions.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu uintptr_t rdn1edge_dmc_base[] = { 13*91f16700Schasinglulu RDN1EDGE_DMC620_BASE0, 14*91f16700Schasinglulu RDN1EDGE_DMC620_BASE1 15*91f16700Schasinglulu }; 16*91f16700Schasinglulu 17*91f16700Schasinglulu static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = { 18*91f16700Schasinglulu .dmc_base = rdn1edge_dmc_base, 19*91f16700Schasinglulu .dmc_count = ARRAY_SIZE(rdn1edge_dmc_base) 20*91f16700Schasinglulu }; 21*91f16700Schasinglulu 22*91f16700Schasinglulu static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = { 23*91f16700Schasinglulu CSS_SGI_DMC620_TZC_REGIONS_DEF 24*91f16700Schasinglulu }; 25*91f16700Schasinglulu 26*91f16700Schasinglulu static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = { 27*91f16700Schasinglulu .plat_drv_data = &rdn1edge_plat_driver_data, 28*91f16700Schasinglulu .plat_acc_addr_data = rdn1edge_acc_addr_data, 29*91f16700Schasinglulu .acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data) 30*91f16700Schasinglulu }; 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* Initialize the secure environment */ 33*91f16700Schasinglulu void plat_arm_security_setup(void) 34*91f16700Schasinglulu { 35*91f16700Schasinglulu arm_tzc_dmc620_setup(&rdn1edge_plat_config_data); 36*91f16700Schasinglulu } 37