1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <drivers/arm/gic600_multichip.h> 9*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 10*91f16700Schasinglulu #include <plat/common/platform.h> 11*91f16700Schasinglulu #include <sgi_soc_platform_def.h> 12*91f16700Schasinglulu #include <sgi_plat.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #if defined(IMAGE_BL31) 15*91f16700Schasinglulu static const mmap_region_t rdn1edge_dynamic_mmap[] = { 16*91f16700Schasinglulu ARM_MAP_SHARED_RAM_REMOTE_CHIP(1), 17*91f16700Schasinglulu CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1), 18*91f16700Schasinglulu SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1) 19*91f16700Schasinglulu }; 20*91f16700Schasinglulu 21*91f16700Schasinglulu static struct gic600_multichip_data rdn1e1_multichip_data __init = { 22*91f16700Schasinglulu .rt_owner_base = PLAT_ARM_GICD_BASE, 23*91f16700Schasinglulu .rt_owner = 0, 24*91f16700Schasinglulu .chip_count = CSS_SGI_CHIP_COUNT, 25*91f16700Schasinglulu .chip_addrs = { 26*91f16700Schasinglulu PLAT_ARM_GICD_BASE >> 16, 27*91f16700Schasinglulu (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16 28*91f16700Schasinglulu }, 29*91f16700Schasinglulu .spi_ids = { 30*91f16700Schasinglulu {PLAT_ARM_GICD_BASE, 32, 255}, 31*91f16700Schasinglulu {0, 0, 0} 32*91f16700Schasinglulu } 33*91f16700Schasinglulu }; 34*91f16700Schasinglulu 35*91f16700Schasinglulu static uintptr_t rdn1e1_multichip_gicr_frames[] = { 36*91f16700Schasinglulu PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */ 37*91f16700Schasinglulu PLAT_ARM_GICR_BASE + 38*91f16700Schasinglulu CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */ 39*91f16700Schasinglulu UL(0) /* Zero Termination */ 40*91f16700Schasinglulu }; 41*91f16700Schasinglulu #endif /* IMAGE_BL31 */ 42*91f16700Schasinglulu 43*91f16700Schasinglulu unsigned int plat_arm_sgi_get_platform_id(void) 44*91f16700Schasinglulu { 45*91f16700Schasinglulu return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) 46*91f16700Schasinglulu & SID_SYSTEM_ID_PART_NUM_MASK; 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu unsigned int plat_arm_sgi_get_config_id(void) 50*91f16700Schasinglulu { 51*91f16700Schasinglulu return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); 52*91f16700Schasinglulu } 53*91f16700Schasinglulu 54*91f16700Schasinglulu unsigned int plat_arm_sgi_get_multi_chip_mode(void) 55*91f16700Schasinglulu { 56*91f16700Schasinglulu return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) & 57*91f16700Schasinglulu SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT; 58*91f16700Schasinglulu } 59*91f16700Schasinglulu 60*91f16700Schasinglulu /* 61*91f16700Schasinglulu * IMAGE_BL31 macro is added to build bl31_platform_setup function only for BL31 62*91f16700Schasinglulu * because PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not 63*91f16700Schasinglulu * for other stages. 64*91f16700Schasinglulu */ 65*91f16700Schasinglulu #if defined(IMAGE_BL31) 66*91f16700Schasinglulu void bl31_platform_setup(void) 67*91f16700Schasinglulu { 68*91f16700Schasinglulu unsigned int i; 69*91f16700Schasinglulu int ret; 70*91f16700Schasinglulu 71*91f16700Schasinglulu if (plat_arm_sgi_get_multi_chip_mode() == 0 && CSS_SGI_CHIP_COUNT > 1) { 72*91f16700Schasinglulu ERROR("Chip Count is set to %d but multi-chip mode not enabled\n", 73*91f16700Schasinglulu CSS_SGI_CHIP_COUNT); 74*91f16700Schasinglulu panic(); 75*91f16700Schasinglulu } else if (plat_arm_sgi_get_multi_chip_mode() == 1 && 76*91f16700Schasinglulu CSS_SGI_CHIP_COUNT > 1) { 77*91f16700Schasinglulu INFO("Enabling support for multi-chip in RD-N1-Edge\n"); 78*91f16700Schasinglulu 79*91f16700Schasinglulu for (i = 0; i < ARRAY_SIZE(rdn1edge_dynamic_mmap); i++) { 80*91f16700Schasinglulu ret = mmap_add_dynamic_region( 81*91f16700Schasinglulu rdn1edge_dynamic_mmap[i].base_pa, 82*91f16700Schasinglulu rdn1edge_dynamic_mmap[i].base_va, 83*91f16700Schasinglulu rdn1edge_dynamic_mmap[i].size, 84*91f16700Schasinglulu rdn1edge_dynamic_mmap[i].attr 85*91f16700Schasinglulu ); 86*91f16700Schasinglulu if (ret != 0) { 87*91f16700Schasinglulu ERROR("Failed to add dynamic mmap entry\n"); 88*91f16700Schasinglulu panic(); 89*91f16700Schasinglulu } 90*91f16700Schasinglulu } 91*91f16700Schasinglulu 92*91f16700Schasinglulu plat_arm_override_gicr_frames(rdn1e1_multichip_gicr_frames); 93*91f16700Schasinglulu gic600_multichip_init(&rdn1e1_multichip_data); 94*91f16700Schasinglulu } 95*91f16700Schasinglulu 96*91f16700Schasinglulu sgi_bl31_common_platform_setup(); 97*91f16700Schasinglulu } 98*91f16700Schasinglulu #endif /* IMAGE_BL31 */ 99