1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu 7*91f16700Schasinglulu$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected) 8*91f16700Schasinglulu 9*91f16700Schasinglulu# GIC-600 configuration 10*91f16700SchasingluluGICV3_IMPL_GIC600_MULTICHIP := 1 11*91f16700Schasinglulu 12*91f16700Schasingluluinclude plat/arm/css/sgi/sgi-common.mk 13*91f16700Schasinglulu 14*91f16700SchasingluluRDN1EDGE_BASE = plat/arm/board/rdn1edge 15*91f16700Schasinglulu 16*91f16700SchasingluluPLAT_INCLUDES += -I${RDN1EDGE_BASE}/include/ 17*91f16700Schasinglulu 18*91f16700SchasingluluSGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S 19*91f16700Schasinglulu 20*91f16700SchasingluluPLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c 21*91f16700Schasinglulu 22*91f16700SchasingluluBL1_SOURCES += ${SGI_CPU_SOURCES} \ 23*91f16700Schasinglulu ${RDN1EDGE_BASE}/rdn1edge_err.c 24*91f16700Schasinglulu 25*91f16700SchasingluluBL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \ 26*91f16700Schasinglulu ${RDN1EDGE_BASE}/rdn1edge_security.c \ 27*91f16700Schasinglulu ${RDN1EDGE_BASE}/rdn1edge_err.c \ 28*91f16700Schasinglulu drivers/arm/tzc/tzc_dmc620.c \ 29*91f16700Schasinglulu lib/utils/mem_region.c \ 30*91f16700Schasinglulu plat/arm/common/arm_nor_psci_mem_protect.c 31*91f16700Schasinglulu 32*91f16700SchasingluluBL31_SOURCES += ${SGI_CPU_SOURCES} \ 33*91f16700Schasinglulu ${RDN1EDGE_BASE}/rdn1edge_plat.c \ 34*91f16700Schasinglulu ${RDN1EDGE_BASE}/rdn1edge_topology.c \ 35*91f16700Schasinglulu drivers/cfi/v2m/v2m_flash.c \ 36*91f16700Schasinglulu lib/utils/mem_region.c \ 37*91f16700Schasinglulu plat/arm/common/arm_nor_psci_mem_protect.c 38*91f16700Schasinglulu 39*91f16700Schasingluluifeq (${TRUSTED_BOARD_BOOT}, 1) 40*91f16700SchasingluluBL1_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c 41*91f16700SchasingluluBL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c 42*91f16700Schasingluluendif 43*91f16700Schasinglulu 44*91f16700Schasinglulu# Enable dynamic addition of MMAP regions in BL31 45*91f16700SchasingluluBL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 46*91f16700Schasinglulu 47*91f16700Schasinglulu# Add the FDT_SOURCES and options for Dynamic Config 48*91f16700SchasingluluFDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \ 49*91f16700Schasinglulu ${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts 50*91f16700SchasingluluFW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 51*91f16700SchasingluluTB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 52*91f16700Schasinglulu 53*91f16700Schasinglulu# Add the FW_CONFIG to FIP and specify the same to certtool 54*91f16700Schasinglulu$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 55*91f16700Schasinglulu# Add the TB_FW_CONFIG to FIP and specify the same to certtool 56*91f16700Schasinglulu$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 57*91f16700Schasinglulu 58*91f16700SchasingluluFDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts 59*91f16700SchasingluluNT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 60*91f16700Schasinglulu 61*91f16700Schasinglulu# Add the NT_FW_CONFIG to FIP and specify the same to certtool 62*91f16700Schasinglulu$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG})) 63*91f16700Schasinglulu 64*91f16700Schasinglulu$(eval $(call CREATE_SEQ,SEQ,2)) 65*91f16700Schasingluluifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ))) 66*91f16700Schasinglulu $(error "Chip count for RDN1Edge platform should be one of $(SEQ), currently \ 67*91f16700Schasinglulu set to ${CSS_SGI_CHIP_COUNT}.") 68*91f16700Schasingluluendif 69*91f16700Schasinglulu 70*91f16700Schasingluluifneq ($(CSS_SGI_PLATFORM_VARIANT),0) 71*91f16700Schasinglulu $(error "CSS_SGI_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \ 72*91f16700Schasinglulu currently set to ${CSS_SGI_PLATFORM_VARIANT}.") 73*91f16700Schasingluluendif 74*91f16700Schasinglulu 75*91f16700Schasingluluoverride CTX_INCLUDE_AARCH32_REGS := 0 76