1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <sgi_sdei.h> 13*91f16700Schasinglulu #include <sgi_soc_platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define PLAT_ARM_CLUSTER_COUNT U(2) 16*91f16700Schasinglulu #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8) 17*91f16700Schasinglulu #define CSS_SGI_MAX_PE_PER_CPU U(2) 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define PLAT_CSS_MHU_BASE UL(0x45400000) 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* Base address of DMC-620 instances */ 22*91f16700Schasinglulu #define RDE1EDGE_DMC620_BASE0 UL(0x4e000000) 23*91f16700Schasinglulu #define RDE1EDGE_DMC620_BASE1 UL(0x4e100000) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* Maximum number of address bits used per chip */ 30*91f16700Schasinglulu #define CSS_SGI_ADDR_BITS_PER_CHIP U(36) 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* 33*91f16700Schasinglulu * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu #ifdef __aarch64__ 36*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) 37*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) 38*91f16700Schasinglulu #else 39*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 40*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 41*91f16700Schasinglulu #endif 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* GIC related constants */ 44*91f16700Schasinglulu #define PLAT_ARM_GICD_BASE UL(0x30000000) 45*91f16700Schasinglulu #define PLAT_ARM_GICC_BASE UL(0x2C000000) 46*91f16700Schasinglulu #define PLAT_ARM_GICR_BASE UL(0x300C0000) 47*91f16700Schasinglulu 48*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 49