1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu /* Topology */ 10*91f16700Schasinglulu typedef struct n1sdp_topology { 11*91f16700Schasinglulu const unsigned char *power_tree; 12*91f16700Schasinglulu unsigned int plat_cluster_core_count; 13*91f16700Schasinglulu } n1sdp_topology_t; 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* 16*91f16700Schasinglulu * The power domain tree descriptor. The cluster power domains are 17*91f16700Schasinglulu * arranged so that when the PSCI generic code creates the power domain tree, 18*91f16700Schasinglulu * the indices of the CPU power domain nodes it allocates match the linear 19*91f16700Schasinglulu * indices returned by plat_core_pos_by_mpidr(). 20*91f16700Schasinglulu */ 21*91f16700Schasinglulu const unsigned char n1sdp_pd_tree_desc[] = { 22*91f16700Schasinglulu PLAT_N1SDP_CHIP_COUNT, 23*91f16700Schasinglulu PLAT_ARM_CLUSTER_COUNT, 24*91f16700Schasinglulu PLAT_ARM_CLUSTER_COUNT, 25*91f16700Schasinglulu N1SDP_MAX_CPUS_PER_CLUSTER, 26*91f16700Schasinglulu N1SDP_MAX_CPUS_PER_CLUSTER, 27*91f16700Schasinglulu N1SDP_MAX_CPUS_PER_CLUSTER, 28*91f16700Schasinglulu N1SDP_MAX_CPUS_PER_CLUSTER 29*91f16700Schasinglulu }; 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* Topology configuration for n1sdp */ 32*91f16700Schasinglulu const n1sdp_topology_t n1sdp_topology = { 33*91f16700Schasinglulu .power_tree = n1sdp_pd_tree_desc, 34*91f16700Schasinglulu .plat_cluster_core_count = N1SDP_MAX_CPUS_PER_CLUSTER 35*91f16700Schasinglulu }; 36*91f16700Schasinglulu 37*91f16700Schasinglulu /******************************************************************************* 38*91f16700Schasinglulu * This function returns the topology tree information. 39*91f16700Schasinglulu ******************************************************************************/ 40*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 41*91f16700Schasinglulu { 42*91f16700Schasinglulu return n1sdp_topology.power_tree; 43*91f16700Schasinglulu } 44*91f16700Schasinglulu 45*91f16700Schasinglulu /******************************************************************************* 46*91f16700Schasinglulu * This function returns the core count within the cluster corresponding to 47*91f16700Schasinglulu * `mpidr`. 48*91f16700Schasinglulu ******************************************************************************/ 49*91f16700Schasinglulu unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 50*91f16700Schasinglulu { 51*91f16700Schasinglulu return n1sdp_topology.plat_cluster_core_count; 52*91f16700Schasinglulu } 53*91f16700Schasinglulu 54*91f16700Schasinglulu /******************************************************************************* 55*91f16700Schasinglulu * The array mapping platform core position (implemented by plat_my_core_pos()) 56*91f16700Schasinglulu * to the SCMI power domain ID implemented by SCP. 57*91f16700Schasinglulu ******************************************************************************/ 58*91f16700Schasinglulu const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = { 59*91f16700Schasinglulu 0, 1, 2, 3, 4, 5, 6, 7}; 60