1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <drivers/arm/sbsa.h> 10*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include "n1sdp_def.h" 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* 15*91f16700Schasinglulu * Table of regions to map using the MMU. 16*91f16700Schasinglulu * Replace or extend the below regions as required 17*91f16700Schasinglulu */ 18*91f16700Schasinglulu 19*91f16700Schasinglulu #if IMAGE_BL1 20*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 21*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 22*91f16700Schasinglulu N1SDP_MAP_DEVICE, 23*91f16700Schasinglulu N1SDP_MAP_NS_SRAM, 24*91f16700Schasinglulu ARM_MAP_DRAM1, 25*91f16700Schasinglulu {0} 26*91f16700Schasinglulu }; 27*91f16700Schasinglulu #endif 28*91f16700Schasinglulu 29*91f16700Schasinglulu #if IMAGE_BL2 30*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 31*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 32*91f16700Schasinglulu N1SDP_MAP_DEVICE, 33*91f16700Schasinglulu N1SDP_MAP_NS_SRAM, 34*91f16700Schasinglulu ARM_MAP_DRAM1, 35*91f16700Schasinglulu ARM_MAP_DRAM2, 36*91f16700Schasinglulu #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 37*91f16700Schasinglulu ARM_MAP_BL1_RW, 38*91f16700Schasinglulu #endif 39*91f16700Schasinglulu {0} 40*91f16700Schasinglulu }; 41*91f16700Schasinglulu #endif 42*91f16700Schasinglulu 43*91f16700Schasinglulu #if IMAGE_BL31 44*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 45*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 46*91f16700Schasinglulu N1SDP_MAP_DEVICE, 47*91f16700Schasinglulu N1SDP_MAP_NS_SRAM, 48*91f16700Schasinglulu N1SDP_MAP_REMOTE_DEVICE, 49*91f16700Schasinglulu N1SDP_MAP_REMOTE_DRAM1, 50*91f16700Schasinglulu N1SDP_MAP_REMOTE_DRAM2, 51*91f16700Schasinglulu {0} 52*91f16700Schasinglulu }; 53*91f16700Schasinglulu #endif 54*91f16700Schasinglulu 55*91f16700Schasinglulu #if TRUSTED_BOARD_BOOT 56*91f16700Schasinglulu int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 57*91f16700Schasinglulu { 58*91f16700Schasinglulu assert(heap_addr != NULL); 59*91f16700Schasinglulu assert(heap_size != NULL); 60*91f16700Schasinglulu 61*91f16700Schasinglulu return arm_get_mbedtls_heap(heap_addr, heap_size); 62*91f16700Schasinglulu } 63*91f16700Schasinglulu #endif 64*91f16700Schasinglulu 65*91f16700Schasinglulu void plat_arm_secure_wdt_start(void) 66*91f16700Schasinglulu { 67*91f16700Schasinglulu sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); 68*91f16700Schasinglulu } 69*91f16700Schasinglulu 70*91f16700Schasinglulu void plat_arm_secure_wdt_stop(void) 71*91f16700Schasinglulu { 72*91f16700Schasinglulu sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); 73*91f16700Schasinglulu } 74