1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2022, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef N1SDP_DEF_H 8*91f16700Schasinglulu #define N1SDP_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Non-secure SRAM MMU mapping */ 11*91f16700Schasinglulu #define N1SDP_NS_SRAM_BASE (0x06000000) 12*91f16700Schasinglulu #define N1SDP_NS_SRAM_SIZE (0x00010000) 13*91f16700Schasinglulu #define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \ 14*91f16700Schasinglulu N1SDP_NS_SRAM_BASE, \ 15*91f16700Schasinglulu N1SDP_NS_SRAM_SIZE, \ 16*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* SDS Platform information defines */ 19*91f16700Schasinglulu #define N1SDP_SDS_PLATFORM_INFO_STRUCT_ID 8 20*91f16700Schasinglulu #define N1SDP_SDS_PLATFORM_INFO_OFFSET 0 21*91f16700Schasinglulu #define N1SDP_SDS_PLATFORM_INFO_SIZE 4 22*91f16700Schasinglulu #define N1SDP_MAX_DDR_CAPACITY_GB 64 23*91f16700Schasinglulu #define N1SDP_MAX_SECONDARY_COUNT 16 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* DMC memory command registers */ 26*91f16700Schasinglulu #define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008 27*91f16700Schasinglulu #define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* DMC ERR0CTLR0 registers */ 30*91f16700Schasinglulu #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 31*91f16700Schasinglulu #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* Remote DMC memory command registers */ 34*91f16700Schasinglulu #define N1SDP_REMOTE_DMC0_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 35*91f16700Schasinglulu N1SDP_DMC0_MEMC_CMD_REG 36*91f16700Schasinglulu #define N1SDP_REMOTE_DMC1_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 37*91f16700Schasinglulu N1SDP_DMC1_MEMC_CMD_REG 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* Remote DMC ERR0CTLR0 registers */ 40*91f16700Schasinglulu #define N1SDP_REMOTE_DMC0_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 41*91f16700Schasinglulu N1SDP_DMC0_ERR0CTLR0_REG 42*91f16700Schasinglulu #define N1SDP_REMOTE_DMC1_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 43*91f16700Schasinglulu N1SDP_DMC1_ERR0CTLR0_REG 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* DMC memory commands */ 46*91f16700Schasinglulu #define N1SDP_DMC_MEMC_CMD_CONFIG 0 47*91f16700Schasinglulu #define N1SDP_DMC_MEMC_CMD_READY 3 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* DMC ECC enable bit in ERR0CTLR0 register */ 50*91f16700Schasinglulu #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 51*91f16700Schasinglulu 52*91f16700Schasinglulu #endif /* N1SDP_DEF_H */ 53