xref: /arm-trusted-firmware/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu/*
2*91f16700Schasinglulu * Copyright (c) 2022 Arm Limited. All rights reserved.
3*91f16700Schasinglulu *
4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu */
6*91f16700Schasinglulu/dts-v1/;
7*91f16700Schasinglulu
8*91f16700Schasinglulu/ {
9*91f16700Schasinglulu	compatible = "arm,ffa-core-manifest-1.0";
10*91f16700Schasinglulu	#address-cells = <2>;
11*91f16700Schasinglulu	#size-cells = <1>;
12*91f16700Schasinglulu
13*91f16700Schasinglulu	/*
14*91f16700Schasinglulu	 * BL32 image details needed by SPMC
15*91f16700Schasinglulu	 *
16*91f16700Schasinglulu	 * Note:
17*91f16700Schasinglulu	 * binary_size: size of BL32 + TOS_FW_CONFIG
18*91f16700Schasinglulu	 */
19*91f16700Schasinglulu
20*91f16700Schasinglulu	attribute {
21*91f16700Schasinglulu		spmc_id = <0x8000>;
22*91f16700Schasinglulu		maj_ver = <0x1>;
23*91f16700Schasinglulu		min_ver = <0x0>;
24*91f16700Schasinglulu		exec_state = <0x0>;
25*91f16700Schasinglulu		load_address = <0x0 0x08000000>;
26*91f16700Schasinglulu		entrypoint = <0x0 0x08000000>;
27*91f16700Schasinglulu		binary_size = <0x2000000>;
28*91f16700Schasinglulu	};
29*91f16700Schasinglulu
30*91f16700Schasinglulu};
31