1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <neoverse_n1.h> 10*91f16700Schasinglulu#include <cpu_macros.S> 11*91f16700Schasinglulu#include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu .globl plat_arm_calc_core_pos 14*91f16700Schasinglulu .globl plat_reset_handler 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* ----------------------------------------------------- 17*91f16700Schasinglulu * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 18*91f16700Schasinglulu * 19*91f16700Schasinglulu * Helper function to calculate the core position. 20*91f16700Schasinglulu * ((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) * 21*91f16700Schasinglulu * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) + 22*91f16700Schasinglulu * (CPUId * N1SDP_MAX_PE_PER_CPU) + ThreadId 23*91f16700Schasinglulu * 24*91f16700Schasinglulu * which can be simplified as: 25*91f16700Schasinglulu * 26*91f16700Schasinglulu * (((ChipId * N1SDP_MAX_CLUSTERS_PER_CHIP + ClusterId) * 27*91f16700Schasinglulu * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * N1SDP_MAX_PE_PER_CPU) + 28*91f16700Schasinglulu * ThreadId 29*91f16700Schasinglulu * ------------------------------------------------------ 30*91f16700Schasinglulu */ 31*91f16700Schasinglulu 32*91f16700Schasinglulufunc plat_arm_calc_core_pos 33*91f16700Schasinglulu mov x4, x0 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* 36*91f16700Schasinglulu * The MT bit in MPIDR is always set for n1sdp and the 37*91f16700Schasinglulu * affinity level 0 corresponds to thread affinity level. 38*91f16700Schasinglulu */ 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* Extract individual affinity fields from MPIDR */ 41*91f16700Schasinglulu ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 42*91f16700Schasinglulu ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 43*91f16700Schasinglulu ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 44*91f16700Schasinglulu ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* Compute linear position */ 47*91f16700Schasinglulu mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP 48*91f16700Schasinglulu madd x2, x3, x4, x2 49*91f16700Schasinglulu mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER 50*91f16700Schasinglulu madd x1, x2, x4, x1 51*91f16700Schasinglulu mov x4, #N1SDP_MAX_PE_PER_CPU 52*91f16700Schasinglulu madd x0, x1, x4, x0 53*91f16700Schasinglulu ret 54*91f16700Schasingluluendfunc plat_arm_calc_core_pos 55*91f16700Schasinglulu 56*91f16700Schasinglulu /* ----------------------------------------------------- 57*91f16700Schasinglulu * void plat_reset_handler(void); 58*91f16700Schasinglulu * 59*91f16700Schasinglulu * Determine the CPU MIDR and disable power down bit for 60*91f16700Schasinglulu * that CPU. 61*91f16700Schasinglulu * ----------------------------------------------------- 62*91f16700Schasinglulu */ 63*91f16700Schasinglulu 64*91f16700Schasinglulufunc plat_reset_handler 65*91f16700Schasinglulu jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 66*91f16700Schasinglulu ret 67*91f16700Schasinglulu 68*91f16700Schasinglulu /* ----------------------------------------------------- 69*91f16700Schasinglulu * Disable CPU power down bit in power control register 70*91f16700Schasinglulu * ----------------------------------------------------- 71*91f16700Schasinglulu */ 72*91f16700SchasingluluN1: 73*91f16700Schasinglulu mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 74*91f16700Schasinglulu bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 75*91f16700Schasinglulu msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 76*91f16700Schasinglulu isb 77*91f16700Schasinglulu ret 78*91f16700Schasingluluendfunc plat_reset_handler 79