1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <lib/cassert.h> 8*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Compile time assertion to ensure the core count is 4 */ 11*91f16700Schasinglulu CASSERT(PLATFORM_CORE_COUNT == 4U, assert_invalid_platform_core_count); 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Topology */ 14*91f16700Schasinglulu typedef struct morello_topology { 15*91f16700Schasinglulu const unsigned char *power_tree; 16*91f16700Schasinglulu unsigned int plat_cluster_core_count; 17*91f16700Schasinglulu } morello_topology_t; 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* 20*91f16700Schasinglulu * The power domain tree descriptor. The cluster power domains are 21*91f16700Schasinglulu * arranged so that when the PSCI generic code creates the power domain tree, 22*91f16700Schasinglulu * the indices of the CPU power domain nodes it allocates match the linear 23*91f16700Schasinglulu * indices returned by plat_core_pos_by_mpidr(). 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu const unsigned char morello_pd_tree_desc[] = { 26*91f16700Schasinglulu PLAT_MORELLO_CHIP_COUNT, 27*91f16700Schasinglulu PLAT_ARM_CLUSTER_COUNT, 28*91f16700Schasinglulu MORELLO_MAX_CPUS_PER_CLUSTER, 29*91f16700Schasinglulu MORELLO_MAX_CPUS_PER_CLUSTER, 30*91f16700Schasinglulu }; 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* Topology configuration for morello */ 33*91f16700Schasinglulu const morello_topology_t morello_topology = { 34*91f16700Schasinglulu .power_tree = morello_pd_tree_desc, 35*91f16700Schasinglulu .plat_cluster_core_count = MORELLO_MAX_CPUS_PER_CLUSTER 36*91f16700Schasinglulu }; 37*91f16700Schasinglulu 38*91f16700Schasinglulu /******************************************************************************* 39*91f16700Schasinglulu * This function returns the topology tree information. 40*91f16700Schasinglulu ******************************************************************************/ 41*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 42*91f16700Schasinglulu { 43*91f16700Schasinglulu return morello_topology.power_tree; 44*91f16700Schasinglulu } 45*91f16700Schasinglulu 46*91f16700Schasinglulu /******************************************************************************* 47*91f16700Schasinglulu * This function returns the core count within the cluster corresponding to 48*91f16700Schasinglulu * `mpidr`. 49*91f16700Schasinglulu ******************************************************************************/ 50*91f16700Schasinglulu unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 51*91f16700Schasinglulu { 52*91f16700Schasinglulu return morello_topology.plat_cluster_core_count; 53*91f16700Schasinglulu } 54*91f16700Schasinglulu 55*91f16700Schasinglulu /******************************************************************************* 56*91f16700Schasinglulu * The array mapping platform core position (implemented by plat_my_core_pos()) 57*91f16700Schasinglulu * to the SCMI power domain ID implemented by SCP. 58*91f16700Schasinglulu ******************************************************************************/ 59*91f16700Schasinglulu const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = { 60*91f16700Schasinglulu 0, 1, 2, 3}; 61