1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <drivers/arm/sbsa.h> 10*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include "morello_def.h" 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* 15*91f16700Schasinglulu * Table of regions to map using the MMU. 16*91f16700Schasinglulu * Replace or extend the below regions as required 17*91f16700Schasinglulu */ 18*91f16700Schasinglulu #if IMAGE_BL1 19*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 20*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 21*91f16700Schasinglulu MORELLO_MAP_DEVICE, 22*91f16700Schasinglulu MORELLO_MAP_NS_SRAM, 23*91f16700Schasinglulu ARM_MAP_DRAM1, 24*91f16700Schasinglulu ARM_MAP_DRAM2, 25*91f16700Schasinglulu {0} 26*91f16700Schasinglulu }; 27*91f16700Schasinglulu #endif 28*91f16700Schasinglulu 29*91f16700Schasinglulu #if IMAGE_BL31 30*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 31*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 32*91f16700Schasinglulu MORELLO_MAP_DEVICE, 33*91f16700Schasinglulu MORELLO_MAP_NS_SRAM, 34*91f16700Schasinglulu {0} 35*91f16700Schasinglulu }; 36*91f16700Schasinglulu #endif 37*91f16700Schasinglulu 38*91f16700Schasinglulu #if IMAGE_BL2 39*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 40*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 41*91f16700Schasinglulu MORELLO_MAP_DEVICE, 42*91f16700Schasinglulu MORELLO_MAP_NS_SRAM, 43*91f16700Schasinglulu ARM_MAP_DRAM1, 44*91f16700Schasinglulu ARM_MAP_DRAM2, 45*91f16700Schasinglulu #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 46*91f16700Schasinglulu ARM_MAP_BL1_RW, 47*91f16700Schasinglulu #endif 48*91f16700Schasinglulu {0} 49*91f16700Schasinglulu }; 50*91f16700Schasinglulu #endif 51*91f16700Schasinglulu 52*91f16700Schasinglulu #if TRUSTED_BOARD_BOOT 53*91f16700Schasinglulu int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu assert(heap_addr != NULL); 56*91f16700Schasinglulu assert(heap_size != NULL); 57*91f16700Schasinglulu 58*91f16700Schasinglulu return arm_get_mbedtls_heap(heap_addr, heap_size); 59*91f16700Schasinglulu } 60*91f16700Schasinglulu #endif 61*91f16700Schasinglulu 62*91f16700Schasinglulu void plat_arm_secure_wdt_start(void) 63*91f16700Schasinglulu { 64*91f16700Schasinglulu sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); 65*91f16700Schasinglulu } 66*91f16700Schasinglulu 67*91f16700Schasinglulu void plat_arm_secure_wdt_stop(void) 68*91f16700Schasinglulu { 69*91f16700Schasinglulu sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); 70*91f16700Schasinglulu } 71