1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2020, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <cpu_macros.S> 10*91f16700Schasinglulu#include <rainier.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu#include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu .globl plat_arm_calc_core_pos 15*91f16700Schasinglulu .globl plat_reset_handler 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* ----------------------------------------------------- 18*91f16700Schasinglulu * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 19*91f16700Schasinglulu * 20*91f16700Schasinglulu * Helper function to calculate the core position. 21*91f16700Schasinglulu * ((ChipId * MORELLO_MAX_CLUSTERS_PER_CHIP + ClusterId) * 22*91f16700Schasinglulu * MORELLO_MAX_CPUS_PER_CLUSTER * MORELLO_MAX_PE_PER_CPU) + 23*91f16700Schasinglulu * (CPUId * MORELLO_MAX_PE_PER_CPU) + ThreadId 24*91f16700Schasinglulu * 25*91f16700Schasinglulu * which can be simplified as: 26*91f16700Schasinglulu * 27*91f16700Schasinglulu * (((ChipId * MORELLO_MAX_CLUSTERS_PER_CHIP + ClusterId) * 28*91f16700Schasinglulu * MORELLO_MAX_CPUS_PER_CLUSTER + CPUId) * MORELLO_MAX_PE_PER_CPU) + 29*91f16700Schasinglulu * ThreadId 30*91f16700Schasinglulu * ------------------------------------------------------ 31*91f16700Schasinglulu */ 32*91f16700Schasinglulu 33*91f16700Schasinglulufunc plat_arm_calc_core_pos 34*91f16700Schasinglulu mov x4, x0 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* 37*91f16700Schasinglulu * The MT bit in MPIDR is always set for morello and the 38*91f16700Schasinglulu * affinity level 0 corresponds to thread affinity level. 39*91f16700Schasinglulu */ 40*91f16700Schasinglulu 41*91f16700Schasinglulu /* Extract individual affinity fields from MPIDR */ 42*91f16700Schasinglulu ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 43*91f16700Schasinglulu ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 44*91f16700Schasinglulu ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 45*91f16700Schasinglulu ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* Compute linear position */ 48*91f16700Schasinglulu mov x4, #MORELLO_MAX_CLUSTERS_PER_CHIP 49*91f16700Schasinglulu madd x2, x3, x4, x2 50*91f16700Schasinglulu mov x4, #MORELLO_MAX_CPUS_PER_CLUSTER 51*91f16700Schasinglulu madd x1, x2, x4, x1 52*91f16700Schasinglulu mov x4, #MORELLO_MAX_PE_PER_CPU 53*91f16700Schasinglulu madd x0, x1, x4, x0 54*91f16700Schasinglulu ret 55*91f16700Schasingluluendfunc plat_arm_calc_core_pos 56