1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef JUNO_TZMP1_DEF_H 8*91f16700Schasinglulu #define JUNO_TZMP1_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* 11*91f16700Schasinglulu * Public memory regions for both protected and non-protected mode 12*91f16700Schasinglulu * 13*91f16700Schasinglulu * OPTEE shared memory 0xFEE00000 - 0xFEFFFFFF 14*91f16700Schasinglulu */ 15*91f16700Schasinglulu #define JUNO_AP_TZC_SHARE_DRAM1_SIZE ULL(0x02000000) 16*91f16700Schasinglulu #define JUNO_AP_TZC_SHARE_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 17*91f16700Schasinglulu JUNO_AP_TZC_SHARE_DRAM1_SIZE) 18*91f16700Schasinglulu #define JUNO_AP_TZC_SHARE_DRAM1_END (ARM_AP_TZC_DRAM1_BASE - 1) 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* ARM_MEDIA_FEATURES for MEDIA GPU Protect Mode Test */ 21*91f16700Schasinglulu #define JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE 8 /* GPU/DPU protected, VPU outbuf */ 22*91f16700Schasinglulu #define JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED 7 /* VPU protected */ 23*91f16700Schasinglulu #define JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE 10 /* VPU private (firmware) */ 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define JUNO_VPU_TZC_PRIV_DRAM1_SIZE ULL(0x02000000) 26*91f16700Schasinglulu #define JUNO_VPU_TZC_PRIV_DRAM1_BASE (JUNO_AP_TZC_SHARE_DRAM1_BASE - \ 27*91f16700Schasinglulu JUNO_VPU_TZC_PRIV_DRAM1_SIZE) 28*91f16700Schasinglulu #define JUNO_VPU_TZC_PRIV_DRAM1_END (JUNO_AP_TZC_SHARE_DRAM1_BASE - 1) 29*91f16700Schasinglulu 30*91f16700Schasinglulu /* Video input protected buffer follows upper item */ 31*91f16700Schasinglulu #define JUNO_VPU_TZC_PROT_DRAM1_SIZE ULL(0x06000000) 32*91f16700Schasinglulu #define JUNO_VPU_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PRIV_DRAM1_BASE - \ 33*91f16700Schasinglulu JUNO_VPU_TZC_PROT_DRAM1_SIZE) 34*91f16700Schasinglulu #define JUNO_VPU_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PRIV_DRAM1_BASE - 1) 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* Video, graphics and display shares same NSAID and same protected buffer */ 37*91f16700Schasinglulu #define JUNO_MEDIA_TZC_PROT_DRAM1_SIZE ULL(0x0e000000) 38*91f16700Schasinglulu #define JUNO_MEDIA_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PROT_DRAM1_BASE - \ 39*91f16700Schasinglulu JUNO_MEDIA_TZC_PROT_DRAM1_SIZE) 40*91f16700Schasinglulu #define JUNO_MEDIA_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PROT_DRAM1_BASE - 1) 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* Rest of DRAM1 are Non-Secure public buffer */ 43*91f16700Schasinglulu #define JUNO_NS_DRAM1_PT1_BASE ARM_DRAM1_BASE 44*91f16700Schasinglulu #define JUNO_NS_DRAM1_PT1_END (JUNO_MEDIA_TZC_PROT_DRAM1_BASE - 1) 45*91f16700Schasinglulu #define JUNO_NS_DRAM1_PT1_SIZE (JUNO_NS_DRAM1_PT1_END - \ 46*91f16700Schasinglulu JUNO_NS_DRAM1_PT1_BASE + 1) 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* TZC filter flags */ 49*91f16700Schasinglulu #define JUNO_MEDIA_TZC_NS_DEV_ACCESS (PLAT_ARM_TZC_NS_DEV_ACCESS | \ 50*91f16700Schasinglulu TZC_REGION_ACCESS_RD(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE)) 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* VPU / GPU /DPU protected access */ 53*91f16700Schasinglulu #define JUNO_MEDIA_TZC_PROT_ACCESS \ 54*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE) | \ 55*91f16700Schasinglulu TZC_REGION_ACCESS_WR(TZC400_NSAID_AP)) 56*91f16700Schasinglulu 57*91f16700Schasinglulu #define JUNO_VPU_TZC_PROT_ACCESS \ 58*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED)) 59*91f16700Schasinglulu 60*91f16700Schasinglulu #define JUNO_VPU_TZC_PRIV_ACCESS \ 61*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE)) 62*91f16700Schasinglulu 63*91f16700Schasinglulu /******************************************************************************* 64*91f16700Schasinglulu * Mali-DP650 related constants 65*91f16700Schasinglulu ******************************************************************************/ 66*91f16700Schasinglulu /* Base address of DP650 */ 67*91f16700Schasinglulu #define DP650_BASE 0x6f200000 68*91f16700Schasinglulu /* offset to PROT_NSAID register */ 69*91f16700Schasinglulu #define DP650_PROT_NSAID_OFFSET 0x10004 70*91f16700Schasinglulu /* config to PROT_NSAID register */ 71*91f16700Schasinglulu #define DP650_PROT_NSAID_CONFIG 0x08008888 72*91f16700Schasinglulu 73*91f16700Schasinglulu /******************************************************************************* 74*91f16700Schasinglulu * Mali-V550 related constants 75*91f16700Schasinglulu ******************************************************************************/ 76*91f16700Schasinglulu /* Base address of V550 */ 77*91f16700Schasinglulu #define V550_BASE 0x6f030000 78*91f16700Schasinglulu /* offset to PROTCTRL register */ 79*91f16700Schasinglulu #define V550_PROTCTRL_OFFSET 0x0040 80*91f16700Schasinglulu /* config to PROTCTRL register */ 81*91f16700Schasinglulu #define V550_PROTCTRL_CONFIG 0xa8700000 82*91f16700Schasinglulu 83*91f16700Schasinglulu #endif /* JUNO_TZMP1_DEF_H */ 84