1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef JUNO_ETHOSN_TZMP1_DEF_H 8*91f16700Schasinglulu #define JUNO_ETHOSN_TZMP1_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define JUNO_ETHOSN_TZC400_NSAID_FW_PROT 7 11*91f16700Schasinglulu #define JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT 8 12*91f16700Schasinglulu #define JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT 13 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* 0 is the default NSAID and is included in PLAT_ARM_TZC_NS_DEV_ACCESS */ 15*91f16700Schasinglulu #define JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS 0 16*91f16700Schasinglulu #define JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS 14 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE UL(0x000400000) /* 4 MB */ 19*91f16700Schasinglulu #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE (ARM_DRAM2_BASE) 20*91f16700Schasinglulu #define JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END (ARM_DRAM2_BASE + \ 21*91f16700Schasinglulu JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE \ 22*91f16700Schasinglulu - 1U) 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_SIZE UL(0x004000000) /* 64 MB */ 25*91f16700Schasinglulu #define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE ( \ 26*91f16700Schasinglulu JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END + 1) 27*91f16700Schasinglulu #define JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END ( \ 28*91f16700Schasinglulu JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE + \ 29*91f16700Schasinglulu JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_SIZE - 1U) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define JUNO_ETHOSN_NS_DRAM2_BASE (JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END + \ 32*91f16700Schasinglulu 1) 33*91f16700Schasinglulu #define JUNO_ETHOSN_NS_DRAM2_END (ARM_DRAM2_END) 34*91f16700Schasinglulu #define JUNO_ETHOSN_NS_DRAM2_SIZE (ARM_DRAM2_SIZE - \ 35*91f16700Schasinglulu JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END) 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define JUNO_FW_TZC_PROT_ACCESS \ 38*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_FW_PROT)) 39*91f16700Schasinglulu #define JUNO_DATA_TZC_PROT_ACCESS \ 40*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT) | \ 41*91f16700Schasinglulu TZC_REGION_ACCESS_RD(JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT)) 42*91f16700Schasinglulu #define JUNO_DATA_TZC_NS_ACCESS \ 43*91f16700Schasinglulu (PLAT_ARM_TZC_NS_DEV_ACCESS | \ 44*91f16700Schasinglulu TZC_REGION_ACCESS_RD(JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS)) 45*91f16700Schasinglulu 46*91f16700Schasinglulu #define JUNO_ETHOSN_TZMP_REGIONS_DEF \ 47*91f16700Schasinglulu { ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE, \ 48*91f16700Schasinglulu TZC_REGION_S_RDWR, 0 }, \ 49*91f16700Schasinglulu { ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, \ 50*91f16700Schasinglulu ARM_TZC_NS_DRAM_S_ACCESS, JUNO_DATA_TZC_NS_ACCESS}, \ 51*91f16700Schasinglulu { JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 52*91f16700Schasinglulu JUNO_ETHOSN_FW_TZC_PROT_DRAM2_END, \ 53*91f16700Schasinglulu TZC_REGION_S_RDWR, JUNO_FW_TZC_PROT_ACCESS }, \ 54*91f16700Schasinglulu { JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_BASE, \ 55*91f16700Schasinglulu JUNO_ETHOSN_DATA_TZC_PROT_DRAM2_END, \ 56*91f16700Schasinglulu TZC_REGION_S_NONE, JUNO_DATA_TZC_PROT_ACCESS }, \ 57*91f16700Schasinglulu { JUNO_ETHOSN_NS_DRAM2_BASE, JUNO_ETHOSN_NS_DRAM2_END, \ 58*91f16700Schasinglulu ARM_TZC_NS_DRAM_S_ACCESS, JUNO_DATA_TZC_NS_ACCESS} 59*91f16700Schasinglulu 60*91f16700Schasinglulu #endif /* JUNO_ETHOSN_TZMP1_DEF_H */ 61