1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef JUNO_DEF_H 8*91f16700Schasinglulu #define JUNO_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /****************************************************************************** 13*91f16700Schasinglulu * Definition of platform soc id 14*91f16700Schasinglulu *****************************************************************************/ 15*91f16700Schasinglulu #define JUNO_SOC_ID 1 16*91f16700Schasinglulu 17*91f16700Schasinglulu /******************************************************************************* 18*91f16700Schasinglulu * Juno memory map related constants 19*91f16700Schasinglulu ******************************************************************************/ 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* Board revisions */ 22*91f16700Schasinglulu #define REV_JUNO_R0 U(0x1) /* Rev B */ 23*91f16700Schasinglulu #define REV_JUNO_R1 U(0x2) /* Rev C */ 24*91f16700Schasinglulu #define REV_JUNO_R2 U(0x3) /* Rev D */ 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* Bypass offset from start of NOR flash */ 27*91f16700Schasinglulu #define BL1_ROM_BYPASS_OFFSET UL(0x03EC0000) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define EMMC_BASE UL(0x0c000000) 30*91f16700Schasinglulu #define EMMC_SIZE UL(0x04000000) 31*91f16700Schasinglulu 32*91f16700Schasinglulu #define PSRAM_BASE UL(0x14000000) 33*91f16700Schasinglulu #define PSRAM_SIZE UL(0x02000000) 34*91f16700Schasinglulu 35*91f16700Schasinglulu #define JUNO_SSC_VER_PART_NUM U(0x030) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /******************************************************************************* 38*91f16700Schasinglulu * Juno topology related constants 39*91f16700Schasinglulu ******************************************************************************/ 40*91f16700Schasinglulu #define JUNO_CLUSTER_COUNT U(2) 41*91f16700Schasinglulu #define JUNO_CLUSTER0_CORE_COUNT U(2) 42*91f16700Schasinglulu #define JUNO_CLUSTER1_CORE_COUNT U(4) 43*91f16700Schasinglulu 44*91f16700Schasinglulu /******************************************************************************* 45*91f16700Schasinglulu * TZC-400 related constants 46*91f16700Schasinglulu ******************************************************************************/ 47*91f16700Schasinglulu #define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ 48*91f16700Schasinglulu #define TZC400_NSAID_PCIE 1 49*91f16700Schasinglulu #define TZC400_NSAID_HDLCD0 2 50*91f16700Schasinglulu #define TZC400_NSAID_HDLCD1 3 51*91f16700Schasinglulu #define TZC400_NSAID_USB 4 52*91f16700Schasinglulu #define TZC400_NSAID_DMA330 5 53*91f16700Schasinglulu #define TZC400_NSAID_THINLINKS 6 54*91f16700Schasinglulu #define TZC400_NSAID_AP 9 55*91f16700Schasinglulu #define TZC400_NSAID_GPU 10 56*91f16700Schasinglulu #define TZC400_NSAID_SCP 11 57*91f16700Schasinglulu #define TZC400_NSAID_CORESIGHT 12 58*91f16700Schasinglulu 59*91f16700Schasinglulu /******************************************************************************* 60*91f16700Schasinglulu * TRNG related constants 61*91f16700Schasinglulu ******************************************************************************/ 62*91f16700Schasinglulu #define TRNG_BASE UL(0x7FE60000) 63*91f16700Schasinglulu #define TRNG_NOUTPUTS 4 64*91f16700Schasinglulu #define TRNG_STATUS UL(0x10) 65*91f16700Schasinglulu #define TRNG_INTMASK UL(0x14) 66*91f16700Schasinglulu #define TRNG_CONFIG UL(0x18) 67*91f16700Schasinglulu #define TRNG_CONTROL UL(0x1C) 68*91f16700Schasinglulu #define TRNG_NBYTES 16 /* Number of bytes generated per round. */ 69*91f16700Schasinglulu 70*91f16700Schasinglulu /******************************************************************************* 71*91f16700Schasinglulu * MMU-401 related constants 72*91f16700Schasinglulu ******************************************************************************/ 73*91f16700Schasinglulu #define MMU401_SSD_OFFSET UL(0x4000) 74*91f16700Schasinglulu #define MMU401_DMA330_BASE UL(0x7fb00000) 75*91f16700Schasinglulu 76*91f16700Schasinglulu /******************************************************************************* 77*91f16700Schasinglulu * Interrupt handling constants 78*91f16700Schasinglulu ******************************************************************************/ 79*91f16700Schasinglulu #define JUNO_IRQ_DMA_SMMU 126 80*91f16700Schasinglulu #define JUNO_IRQ_HDLCD0_SMMU 128 81*91f16700Schasinglulu #define JUNO_IRQ_HDLCD1_SMMU 130 82*91f16700Schasinglulu #define JUNO_IRQ_USB_SMMU 132 83*91f16700Schasinglulu #define JUNO_IRQ_THIN_LINKS_SMMU 134 84*91f16700Schasinglulu #define JUNO_IRQ_SEC_I2C 137 85*91f16700Schasinglulu #define JUNO_IRQ_GPU_SMMU_1 73 86*91f16700Schasinglulu #define JUNO_IRQ_ETR_SMMU 75 87*91f16700Schasinglulu 88*91f16700Schasinglulu /******************************************************************************* 89*91f16700Schasinglulu * Memprotect definitions 90*91f16700Schasinglulu ******************************************************************************/ 91*91f16700Schasinglulu /* PSCI memory protect definitions: 92*91f16700Schasinglulu * This variable is stored in a non-secure flash because some ARM reference 93*91f16700Schasinglulu * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 94*91f16700Schasinglulu * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 95*91f16700Schasinglulu */ 96*91f16700Schasinglulu #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 97*91f16700Schasinglulu V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 98*91f16700Schasinglulu 99*91f16700Schasinglulu #endif /* JUNO_DEF_H */ 100