xref: /arm-trusted-firmware/plat/arm/board/juno/juno_common.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #include <lib/smccc.h>
8*91f16700Schasinglulu #include <platform_def.h>
9*91f16700Schasinglulu #include <services/arm_arch_svc.h>
10*91f16700Schasinglulu 
11*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h>
12*91f16700Schasinglulu 
13*91f16700Schasinglulu /*
14*91f16700Schasinglulu  * Table of memory regions for different BL stages to map using the MMU.
15*91f16700Schasinglulu  * This doesn't include Trusted SRAM as setup_page_tables() already takes care
16*91f16700Schasinglulu  * of mapping it.
17*91f16700Schasinglulu  */
18*91f16700Schasinglulu #ifdef IMAGE_BL1
19*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = {
20*91f16700Schasinglulu 	ARM_MAP_SHARED_RAM,
21*91f16700Schasinglulu 	V2M_MAP_FLASH0_RW,
22*91f16700Schasinglulu 	V2M_MAP_IOFPGA,
23*91f16700Schasinglulu 	CSS_MAP_DEVICE,
24*91f16700Schasinglulu 	SOC_CSS_MAP_DEVICE,
25*91f16700Schasinglulu #if TRUSTED_BOARD_BOOT
26*91f16700Schasinglulu 	/* Map DRAM to authenticate NS_BL2U image. */
27*91f16700Schasinglulu 	ARM_MAP_NS_DRAM1,
28*91f16700Schasinglulu #endif
29*91f16700Schasinglulu 	{0}
30*91f16700Schasinglulu };
31*91f16700Schasinglulu #endif
32*91f16700Schasinglulu #ifdef IMAGE_BL2
33*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = {
34*91f16700Schasinglulu 	ARM_MAP_SHARED_RAM,
35*91f16700Schasinglulu 	V2M_MAP_FLASH0_RW,
36*91f16700Schasinglulu #ifdef PLAT_ARM_MEM_PROT_ADDR
37*91f16700Schasinglulu 	ARM_V2M_MAP_MEM_PROTECT,
38*91f16700Schasinglulu #endif
39*91f16700Schasinglulu 	V2M_MAP_IOFPGA,
40*91f16700Schasinglulu 	CSS_MAP_DEVICE,
41*91f16700Schasinglulu 	SOC_CSS_MAP_DEVICE,
42*91f16700Schasinglulu 	ARM_MAP_NS_DRAM1,
43*91f16700Schasinglulu #ifdef __aarch64__
44*91f16700Schasinglulu 	ARM_MAP_DRAM2,
45*91f16700Schasinglulu #endif
46*91f16700Schasinglulu #ifdef SPD_tspd
47*91f16700Schasinglulu 	ARM_MAP_TSP_SEC_MEM,
48*91f16700Schasinglulu #endif
49*91f16700Schasinglulu #ifdef SPD_opteed
50*91f16700Schasinglulu 	ARM_MAP_OPTEE_CORE_MEM,
51*91f16700Schasinglulu 	ARM_OPTEE_PAGEABLE_LOAD_MEM,
52*91f16700Schasinglulu #endif
53*91f16700Schasinglulu #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
54*91f16700Schasinglulu 	ARM_MAP_BL1_RW,
55*91f16700Schasinglulu #endif
56*91f16700Schasinglulu #ifdef JUNO_ETHOSN_TZMP1
57*91f16700Schasinglulu 	JUNO_ETHOSN_PROT_FW_RW,
58*91f16700Schasinglulu #endif
59*91f16700Schasinglulu 	{0}
60*91f16700Schasinglulu };
61*91f16700Schasinglulu #endif
62*91f16700Schasinglulu #ifdef IMAGE_BL2U
63*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = {
64*91f16700Schasinglulu 	ARM_MAP_SHARED_RAM,
65*91f16700Schasinglulu 	CSS_MAP_DEVICE,
66*91f16700Schasinglulu 	CSS_MAP_SCP_BL2U,
67*91f16700Schasinglulu 	V2M_MAP_IOFPGA,
68*91f16700Schasinglulu 	SOC_CSS_MAP_DEVICE,
69*91f16700Schasinglulu 	{0}
70*91f16700Schasinglulu };
71*91f16700Schasinglulu #endif
72*91f16700Schasinglulu #ifdef IMAGE_BL31
73*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = {
74*91f16700Schasinglulu 	ARM_MAP_SHARED_RAM,
75*91f16700Schasinglulu 	V2M_MAP_IOFPGA,
76*91f16700Schasinglulu 	CSS_MAP_DEVICE,
77*91f16700Schasinglulu #ifdef PLAT_ARM_MEM_PROT_ADDR
78*91f16700Schasinglulu 	ARM_V2M_MAP_MEM_PROTECT,
79*91f16700Schasinglulu #endif
80*91f16700Schasinglulu 	SOC_CSS_MAP_DEVICE,
81*91f16700Schasinglulu 	ARM_DTB_DRAM_NS,
82*91f16700Schasinglulu #ifdef JUNO_ETHOSN_TZMP1
83*91f16700Schasinglulu 	JUNO_ETHOSN_PROT_FW_RO,
84*91f16700Schasinglulu #endif
85*91f16700Schasinglulu 	{0}
86*91f16700Schasinglulu };
87*91f16700Schasinglulu #endif
88*91f16700Schasinglulu #ifdef IMAGE_BL32
89*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = {
90*91f16700Schasinglulu #ifndef __aarch64__
91*91f16700Schasinglulu 	ARM_MAP_SHARED_RAM,
92*91f16700Schasinglulu #ifdef PLAT_ARM_MEM_PROT_ADDR
93*91f16700Schasinglulu 	ARM_V2M_MAP_MEM_PROTECT,
94*91f16700Schasinglulu #endif
95*91f16700Schasinglulu #endif
96*91f16700Schasinglulu 	V2M_MAP_IOFPGA,
97*91f16700Schasinglulu 	CSS_MAP_DEVICE,
98*91f16700Schasinglulu 	SOC_CSS_MAP_DEVICE,
99*91f16700Schasinglulu 	{0}
100*91f16700Schasinglulu };
101*91f16700Schasinglulu #endif
102*91f16700Schasinglulu 
103*91f16700Schasinglulu ARM_CASSERT_MMAP
104*91f16700Schasinglulu 
105*91f16700Schasinglulu /*****************************************************************************
106*91f16700Schasinglulu  * plat_is_smccc_feature_available() - This function checks whether SMCCC
107*91f16700Schasinglulu  *                                     feature is availabile for platform.
108*91f16700Schasinglulu  * @fid: SMCCC function id
109*91f16700Schasinglulu  *
110*91f16700Schasinglulu  * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
111*91f16700Schasinglulu  * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
112*91f16700Schasinglulu  *****************************************************************************/
113*91f16700Schasinglulu int32_t plat_is_smccc_feature_available(u_register_t fid)
114*91f16700Schasinglulu {
115*91f16700Schasinglulu 	switch (fid) {
116*91f16700Schasinglulu 	case SMCCC_ARCH_SOC_ID:
117*91f16700Schasinglulu 		return SMC_ARCH_CALL_SUCCESS;
118*91f16700Schasinglulu 	default:
119*91f16700Schasinglulu 		return SMC_ARCH_CALL_NOT_SUPPORTED;
120*91f16700Schasinglulu 	}
121*91f16700Schasinglulu }
122*91f16700Schasinglulu 
123*91f16700Schasinglulu /* Get SOC version */
124*91f16700Schasinglulu int32_t plat_get_soc_version(void)
125*91f16700Schasinglulu {
126*91f16700Schasinglulu 	return (int32_t)
127*91f16700Schasinglulu 		(SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
128*91f16700Schasinglulu 				    ARM_SOC_IDENTIFICATION_CODE) |
129*91f16700Schasinglulu 		 (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK));
130*91f16700Schasinglulu }
131*91f16700Schasinglulu 
132*91f16700Schasinglulu /* Get SOC revision */
133*91f16700Schasinglulu int32_t plat_get_soc_revision(void)
134*91f16700Schasinglulu {
135*91f16700Schasinglulu 	unsigned int sys_id;
136*91f16700Schasinglulu 
137*91f16700Schasinglulu 	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
138*91f16700Schasinglulu 	return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
139*91f16700Schasinglulu 			  V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
140*91f16700Schasinglulu }
141