1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <lib/fconf/fconf.h> 11*91f16700Schasinglulu #include <lib/fconf/fconf_dyn_cfg_getter.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu void __init bl31_early_platform_setup2(u_register_t arg0, 16*91f16700Schasinglulu u_register_t arg1, u_register_t arg2, u_register_t arg3) 17*91f16700Schasinglulu { 18*91f16700Schasinglulu const struct dyn_cfg_dtb_info_t *soc_fw_config_info; 19*91f16700Schasinglulu 20*91f16700Schasinglulu INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* Fill the properties struct with the info from the config dtb */ 23*91f16700Schasinglulu fconf_populate("FW_CONFIG", arg1); 24*91f16700Schasinglulu 25*91f16700Schasinglulu soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID); 26*91f16700Schasinglulu if (soc_fw_config_info != NULL) { 27*91f16700Schasinglulu arg1 = soc_fw_config_info->config_addr; 28*91f16700Schasinglulu } 29*91f16700Schasinglulu 30*91f16700Schasinglulu arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* 33*91f16700Schasinglulu * Initialize Interconnect for this cluster during cold boot. 34*91f16700Schasinglulu * No need for locks as no other CPU is active. 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu plat_arm_interconnect_init(); 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* 39*91f16700Schasinglulu * Enable Interconnect coherency for the primary CPU's cluster. 40*91f16700Schasinglulu * Earlier bootloader stages might already do this (e.g. Trusted 41*91f16700Schasinglulu * Firmware's BL1 does it) but we can't assume so. There is no harm in 42*91f16700Schasinglulu * executing this code twice anyway. 43*91f16700Schasinglulu * Platform specific PSCI code will enable coherency for other 44*91f16700Schasinglulu * clusters. 45*91f16700Schasinglulu */ 46*91f16700Schasinglulu plat_arm_interconnect_enter_coherency(); 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu void __init bl31_plat_arch_setup(void) 50*91f16700Schasinglulu { 51*91f16700Schasinglulu arm_bl31_plat_arch_setup(); 52*91f16700Schasinglulu 53*91f16700Schasinglulu /* HW_CONFIG was also loaded by BL2 */ 54*91f16700Schasinglulu const struct dyn_cfg_dtb_info_t *hw_config_info; 55*91f16700Schasinglulu 56*91f16700Schasinglulu hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 57*91f16700Schasinglulu assert(hw_config_info != NULL); 58*91f16700Schasinglulu 59*91f16700Schasinglulu fconf_populate("HW_CONFIG", hw_config_info->config_addr); 60*91f16700Schasinglulu } 61