1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef FVP_VE_DEF_H 8*91f16700Schasinglulu #define FVP_VE_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Default cluster count for FVP VE */ 13*91f16700Schasinglulu #define FVP_VE_CLUSTER_COUNT U(1) 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Default number of CPUs per cluster on FVP VE */ 16*91f16700Schasinglulu #define FVP_VE_MAX_CPUS_PER_CLUSTER U(1) 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* Default number of threads per CPU on FVP VE */ 19*91f16700Schasinglulu #define FVP_VE_MAX_PE_PER_CPU U(1) 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define FVP_VE_CORE_COUNT U(1) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define FVP_VE_PRIMARY_CPU 0x0 24*91f16700Schasinglulu 25*91f16700Schasinglulu /******************************************************************************* 26*91f16700Schasinglulu * FVP memory map related constants 27*91f16700Schasinglulu ******************************************************************************/ 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define FLASH1_BASE 0x0c000000 30*91f16700Schasinglulu #define FLASH1_SIZE 0x04000000 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* Aggregate of all devices in the first GB */ 33*91f16700Schasinglulu #define DEVICE0_BASE 0x20000000 34*91f16700Schasinglulu #define DEVICE0_SIZE 0x0c200000 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define NSRAM_BASE 0x2e000000 37*91f16700Schasinglulu #define NSRAM_SIZE 0x10000 38*91f16700Schasinglulu 39*91f16700Schasinglulu #define PCIE_EXP_BASE 0x40000000 40*91f16700Schasinglulu #define TZRNG_BASE 0x7fe60000 41*91f16700Schasinglulu 42*91f16700Schasinglulu #define ARCH_MODEL_VE 0x5 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* FVP Power controller base address*/ 45*91f16700Schasinglulu #define PWRC_BASE UL(0x1c100000) 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* FVP SP804 timer frequency is 35 MHz*/ 48*91f16700Schasinglulu #define SP804_TIMER_CLKMULT 1 49*91f16700Schasinglulu #define SP804_TIMER_CLKDIV 35 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* SP810 controller. FVP specific flags */ 52*91f16700Schasinglulu #define FVP_SP810_CTRL_TIM0_OV (1 << 16) 53*91f16700Schasinglulu #define FVP_SP810_CTRL_TIM1_OV (1 << 18) 54*91f16700Schasinglulu #define FVP_SP810_CTRL_TIM2_OV (1 << 20) 55*91f16700Schasinglulu #define FVP_SP810_CTRL_TIM3_OV (1 << 22) 56*91f16700Schasinglulu 57*91f16700Schasinglulu /******************************************************************************* 58*91f16700Schasinglulu * GIC-400 & interrupt handling related constants 59*91f16700Schasinglulu ******************************************************************************/ 60*91f16700Schasinglulu /* VE compatible GIC memory map */ 61*91f16700Schasinglulu #define VE_GICD_BASE 0x2c001000 62*91f16700Schasinglulu #ifdef ARM_CORTEX_A5 63*91f16700Schasinglulu #define VE_GICC_BASE 0x2c000100 64*91f16700Schasinglulu #else 65*91f16700Schasinglulu #define VE_GICC_BASE 0x2c002000 66*91f16700Schasinglulu #endif 67*91f16700Schasinglulu #define VE_GICH_BASE 0x2c004000 68*91f16700Schasinglulu #define VE_GICV_BASE 0x2c006000 69*91f16700Schasinglulu 70*91f16700Schasinglulu #define FVP_VE_IRQ_TZ_WDOG 56 71*91f16700Schasinglulu #define FVP_VE_IRQ_SEC_SYS_TIMER 57 72*91f16700Schasinglulu 73*91f16700Schasinglulu #define V2M_FLASH1_BASE UL(0x0C000000) 74*91f16700Schasinglulu #define V2M_FLASH1_SIZE UL(0x04000000) 75*91f16700Schasinglulu 76*91f16700Schasinglulu #define V2M_MAP_FLASH1_RW MAP_REGION_FLAT(V2M_FLASH1_BASE,\ 77*91f16700Schasinglulu V2M_FLASH1_SIZE, \ 78*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 79*91f16700Schasinglulu 80*91f16700Schasinglulu #define V2M_MAP_FLASH1_RO MAP_REGION_FLAT(V2M_FLASH1_BASE,\ 81*91f16700Schasinglulu V2M_FLASH1_SIZE, \ 82*91f16700Schasinglulu MT_RO_DATA | MT_SECURE) 83*91f16700Schasinglulu 84*91f16700Schasinglulu #endif /* FVP_VE_DEF_H */ 85