1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu #include <plat/arm/common/arm_config.h> 13*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 16*91f16700Schasinglulu DEVICE0_SIZE, \ 17*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 18*91f16700Schasinglulu 19*91f16700Schasinglulu #ifdef IMAGE_BL1 20*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 21*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 22*91f16700Schasinglulu V2M_MAP_FLASH1_RW, 23*91f16700Schasinglulu V2M_MAP_IOFPGA, 24*91f16700Schasinglulu {0} 25*91f16700Schasinglulu }; 26*91f16700Schasinglulu #endif 27*91f16700Schasinglulu #ifdef IMAGE_BL2 28*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 29*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 30*91f16700Schasinglulu V2M_MAP_FLASH1_RW, 31*91f16700Schasinglulu V2M_MAP_IOFPGA, 32*91f16700Schasinglulu ARM_MAP_NS_DRAM1, 33*91f16700Schasinglulu {0} 34*91f16700Schasinglulu }; 35*91f16700Schasinglulu #endif 36*91f16700Schasinglulu #ifdef IMAGE_BL32 37*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 38*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 39*91f16700Schasinglulu V2M_MAP_IOFPGA, 40*91f16700Schasinglulu MAP_DEVICE0, 41*91f16700Schasinglulu {0} 42*91f16700Schasinglulu }; 43*91f16700Schasinglulu #endif 44*91f16700Schasinglulu 45*91f16700Schasinglulu ARM_CASSERT_MMAP 46*91f16700Schasinglulu 47*91f16700Schasinglulu void __init fvp_ve_config_setup(void) 48*91f16700Schasinglulu { 49*91f16700Schasinglulu unsigned int sys_id, arch; 50*91f16700Schasinglulu 51*91f16700Schasinglulu sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 52*91f16700Schasinglulu arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 53*91f16700Schasinglulu 54*91f16700Schasinglulu if (arch != ARCH_MODEL_VE) { 55*91f16700Schasinglulu ERROR("This firmware is for FVP VE models\n"); 56*91f16700Schasinglulu panic(); 57*91f16700Schasinglulu } 58*91f16700Schasinglulu } 59*91f16700Schasinglulu 60*91f16700Schasinglulu unsigned int plat_get_syscnt_freq2(void) 61*91f16700Schasinglulu { 62*91f16700Schasinglulu return FVP_VE_TIMER_BASE_FREQUENCY; 63*91f16700Schasinglulu } 64