1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <drivers/arm/sp804_delay_timer.h> 8*91f16700Schasinglulu #include <drivers/generic_delay_timer.h> 9*91f16700Schasinglulu #include <lib/mmio.h> 10*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 11*91f16700Schasinglulu #include <plat/common/platform.h> 12*91f16700Schasinglulu #include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include "fvp_ve_private.h" 15*91f16700Schasinglulu 16*91f16700Schasinglulu void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 17*91f16700Schasinglulu { 18*91f16700Schasinglulu arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* Initialize the platform config for future decision making */ 21*91f16700Schasinglulu fvp_ve_config_setup(); 22*91f16700Schasinglulu } 23*91f16700Schasinglulu 24*91f16700Schasinglulu void bl2_platform_setup(void) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu arm_bl2_platform_setup(); 27*91f16700Schasinglulu 28*91f16700Schasinglulu #if USE_SP804_TIMER 29*91f16700Schasinglulu /* 30*91f16700Schasinglulu * Enable the clock override for SP804 timer 0, which means that no 31*91f16700Schasinglulu * clock dividers are applied and the raw (35 MHz) clock will be used 32*91f16700Schasinglulu */ 33*91f16700Schasinglulu mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* Initialize delay timer driver using SP804 dual timer 0 */ 36*91f16700Schasinglulu sp804_timer_init(V2M_SP804_TIMER0_BASE, 37*91f16700Schasinglulu SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 38*91f16700Schasinglulu #else 39*91f16700Schasinglulu generic_delay_timer_init(); 40*91f16700Schasinglulu #endif /* USE_SP804_TIMER */ 41*91f16700Schasinglulu } 42*91f16700Schasinglulu 43*91f16700Schasinglulu int bl2_plat_handle_post_image_load(unsigned int image_id) 44*91f16700Schasinglulu { 45*91f16700Schasinglulu return arm_bl2_plat_handle_post_image_load(image_id); 46*91f16700Schasinglulu } 47