1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2019, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl plat_secondary_cold_boot_setup 12*91f16700Schasinglulu .globl plat_get_my_entrypoint 13*91f16700Schasinglulu .globl plat_is_my_cpu_primary 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* -------------------------------------------------------------------- 16*91f16700Schasinglulu * void plat_secondary_cold_boot_setup (void); 17*91f16700Schasinglulu * 18*91f16700Schasinglulu * For AArch32, cold-booting secondary CPUs is not yet 19*91f16700Schasinglulu * implemented and they panic. 20*91f16700Schasinglulu * -------------------------------------------------------------------- 21*91f16700Schasinglulu */ 22*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 23*91f16700Schasinglulucb_panic: 24*91f16700Schasinglulu b cb_panic 25*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* --------------------------------------------------------------------- 28*91f16700Schasinglulu * unsigned long plat_get_my_entrypoint (void); 29*91f16700Schasinglulu * 30*91f16700Schasinglulu * Main job of this routine is to distinguish between a cold and warm 31*91f16700Schasinglulu * boot. On FVP, this information can be queried from the power 32*91f16700Schasinglulu * controller. The Power Control SYS Status Register (PSYSR) indicates 33*91f16700Schasinglulu * the wake-up reason for the CPU. 34*91f16700Schasinglulu * 35*91f16700Schasinglulu * For a cold boot, return 0. 36*91f16700Schasinglulu * For a warm boot, read the mailbox and return the address it contains. 37*91f16700Schasinglulu * 38*91f16700Schasinglulu * TODO: PSYSR is a common register and should be 39*91f16700Schasinglulu * accessed using locks. Since it is not possible 40*91f16700Schasinglulu * to use locks immediately after a cold reset 41*91f16700Schasinglulu * we are relying on the fact that after a cold 42*91f16700Schasinglulu * reset all cpus will read the same WK field 43*91f16700Schasinglulu * --------------------------------------------------------------------- 44*91f16700Schasinglulu */ 45*91f16700Schasinglulufunc plat_get_my_entrypoint 46*91f16700Schasinglulu /* TODO support warm boot */ 47*91f16700Schasinglulu /* Cold reset */ 48*91f16700Schasinglulu mov r0, #0 49*91f16700Schasinglulu bx lr 50*91f16700Schasinglulu 51*91f16700Schasingluluendfunc plat_get_my_entrypoint 52*91f16700Schasinglulu 53*91f16700Schasinglulu /* ----------------------------------------------------- 54*91f16700Schasinglulu * unsigned int plat_is_my_cpu_primary (void); 55*91f16700Schasinglulu * 56*91f16700Schasinglulu * Currently configured for a sigle CPU 57*91f16700Schasinglulu * ----------------------------------------------------- 58*91f16700Schasinglulu */ 59*91f16700Schasinglulufunc plat_is_my_cpu_primary 60*91f16700Schasinglulu mov r0, #1 61*91f16700Schasinglulu bx lr 62*91f16700Schasingluluendfunc plat_is_my_cpu_primary 63