1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef FVP_R_ARCH_HELPERS_H 8*91f16700Schasinglulu #define FVP_R_ARCH_HELPERS_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch_helpers.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /******************************************************************************* 13*91f16700Schasinglulu * MPU register definitions 14*91f16700Schasinglulu ******************************************************************************/ 15*91f16700Schasinglulu #define MPUIR_EL2 S3_4_C0_C0_4 16*91f16700Schasinglulu #define PRBAR_EL2 S3_4_C6_C8_0 17*91f16700Schasinglulu #define PRLAR_EL2 S3_4_C6_C8_1 18*91f16700Schasinglulu #define PRSELR_EL2 S3_4_C6_C2_1 19*91f16700Schasinglulu #define PRENR_EL2 S3_4_C6_C1_1 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* v8-R64 MPU registers */ 22*91f16700Schasinglulu DEFINE_RENAME_SYSREG_RW_FUNCS(mpuir_el2, MPUIR_EL2) 23*91f16700Schasinglulu DEFINE_RENAME_SYSREG_RW_FUNCS(prenr_el2, PRENR_EL2) 24*91f16700Schasinglulu DEFINE_RENAME_SYSREG_RW_FUNCS(prselr_el2, PRSELR_EL2) 25*91f16700Schasinglulu DEFINE_RENAME_SYSREG_RW_FUNCS(prbar_el2, PRBAR_EL2) 26*91f16700Schasinglulu DEFINE_RENAME_SYSREG_RW_FUNCS(prlar_el2, PRLAR_EL2) 27*91f16700Schasinglulu 28*91f16700Schasinglulu #endif /* FVP_R_ARCH_HELPERS_H */ 29