1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch_helpers.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu /************************************************************ 10*91f16700Schasinglulu * For R-class everything is in secure world. 11*91f16700Schasinglulu * Prepare the CPU system registers for first entry into EL1 12*91f16700Schasinglulu ************************************************************/ 13*91f16700Schasinglulu void cm_prepare_el2_exit(void) 14*91f16700Schasinglulu { 15*91f16700Schasinglulu uint64_t hcr_el2 = 0U; 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* 18*91f16700Schasinglulu * The use of ARMv8.3 pointer authentication (PAuth) is governed 19*91f16700Schasinglulu * by fields in HCR_EL2, which trigger a 'trap to EL2' if not 20*91f16700Schasinglulu * enabled. This register initialized at boot up, update PAuth 21*91f16700Schasinglulu * bits. 22*91f16700Schasinglulu * 23*91f16700Schasinglulu * HCR_API_BIT: Set to one to disable traps to EL2 if lower ELs 24*91f16700Schasinglulu * access PAuth registers 25*91f16700Schasinglulu * 26*91f16700Schasinglulu * HCR_APK_BIT: Set to one to disable traps to EL2 if lower ELs 27*91f16700Schasinglulu * access PAuth instructions 28*91f16700Schasinglulu */ 29*91f16700Schasinglulu hcr_el2 = read_hcr_el2(); 30*91f16700Schasinglulu write_hcr_el2(hcr_el2 | HCR_API_BIT | HCR_APK_BIT); 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* 33*91f16700Schasinglulu * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN 34*91f16700Schasinglulu * on reset and are set to zero except for field(s) listed below. 35*91f16700Schasinglulu * 36*91f16700Schasinglulu * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to EL2 37*91f16700Schasinglulu * if lower ELs accesses to the physical timer registers. 38*91f16700Schasinglulu * 39*91f16700Schasinglulu * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to EL2 40*91f16700Schasinglulu * if lower ELs access to the physical counter registers. 41*91f16700Schasinglulu */ 42*91f16700Schasinglulu write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* 45*91f16700Schasinglulu * On Armv8-R, the EL1&0 memory system architecture is configurable 46*91f16700Schasinglulu * as a VMSA or PMSA. All the fields architecturally UNKNOWN on reset 47*91f16700Schasinglulu * and are set to zero except for field listed below. 48*91f16700Schasinglulu * 49*91f16700Schasinglulu * VCTR_EL2.MSA: Set to one to ensure the VMSA is enabled so that 50*91f16700Schasinglulu * rich OS can boot. 51*91f16700Schasinglulu */ 52*91f16700Schasinglulu write_vtcr_el2(VTCR_RESET_VAL | VTCR_EL2_MSA); 53*91f16700Schasinglulu } 54