1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <common/bl_common.h> 10*91f16700Schasinglulu#include <el2_common_macros.S> 11*91f16700Schasinglulu#include <lib/xlat_mpu/xlat_mpu.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu .globl bl1_entrypoint 14*91f16700Schasinglulu .globl bl1_run_next_image 15*91f16700Schasinglulu 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* ----------------------------------------------------- 18*91f16700Schasinglulu * bl1_entrypoint() is the entry point into the trusted 19*91f16700Schasinglulu * firmware code when a cpu is released from warm or 20*91f16700Schasinglulu * cold reset. 21*91f16700Schasinglulu * ----------------------------------------------------- 22*91f16700Schasinglulu */ 23*91f16700Schasinglulu 24*91f16700Schasinglulufunc bl1_entrypoint 25*91f16700Schasinglulu /* --------------------------------------------------------------------- 26*91f16700Schasinglulu * If the reset address is programmable then bl1_entrypoint() is 27*91f16700Schasinglulu * executed only on the cold boot path. Therefore, we can skip the warm 28*91f16700Schasinglulu * boot mailbox mechanism. 29*91f16700Schasinglulu * --------------------------------------------------------------------- 30*91f16700Schasinglulu */ 31*91f16700Schasinglulu el2_entrypoint_common \ 32*91f16700Schasinglulu _init_sctlr=1 \ 33*91f16700Schasinglulu _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 34*91f16700Schasinglulu _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 35*91f16700Schasinglulu _init_memory=1 \ 36*91f16700Schasinglulu _init_c_runtime=1 \ 37*91f16700Schasinglulu _exception_vectors=bl1_exceptions \ 38*91f16700Schasinglulu _pie_fixup_size=0 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* -------------------------------------------------------------------- 41*91f16700Schasinglulu * Perform BL1 setup 42*91f16700Schasinglulu * -------------------------------------------------------------------- 43*91f16700Schasinglulu */ 44*91f16700Schasinglulu bl bl1_setup 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* -------------------------------------------------------------------- 47*91f16700Schasinglulu * Initialize platform and jump to our c-entry point 48*91f16700Schasinglulu * for this type of reset. 49*91f16700Schasinglulu * -------------------------------------------------------------------- 50*91f16700Schasinglulu */ 51*91f16700Schasinglulu bl bl1_main 52*91f16700Schasinglulu 53*91f16700Schasinglulu /* --------------------------------------------- 54*91f16700Schasinglulu * Should never reach this point. 55*91f16700Schasinglulu * --------------------------------------------- 56*91f16700Schasinglulu */ 57*91f16700Schasinglulu no_ret plat_panic_handler 58*91f16700Schasingluluendfunc bl1_entrypoint 59*91f16700Schasinglulu 60*91f16700Schasinglulufunc bl1_run_next_image 61*91f16700Schasinglulu mov x20,x0 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* --------------------------------------------- 64*91f16700Schasinglulu * MPU needs to be disabled because both BL1 and BL33 execute 65*91f16700Schasinglulu * in EL2, and therefore share the same address space. 66*91f16700Schasinglulu * BL33 will initialize the address space according to its 67*91f16700Schasinglulu * own requirement. 68*91f16700Schasinglulu * --------------------------------------------- 69*91f16700Schasinglulu */ 70*91f16700Schasinglulu bl disable_mpu_icache_el2 71*91f16700Schasinglulu 72*91f16700Schasinglulu /* --------------------------------------------- 73*91f16700Schasinglulu * Wipe clean and disable all MPU regions. This function expects 74*91f16700Schasinglulu * that the MPU has already been turned off, and caching concerns 75*91f16700Schasinglulu * addressed, but it also explicitly turns off the MPU. 76*91f16700Schasinglulu * --------------------------------------------- 77*91f16700Schasinglulu */ 78*91f16700Schasinglulu bl clear_all_mpu_regions 79*91f16700Schasinglulu 80*91f16700Schasinglulu /* -------------------------------------------------- 81*91f16700Schasinglulu * Do the transition to next boot image. 82*91f16700Schasinglulu * -------------------------------------------------- 83*91f16700Schasinglulu */ 84*91f16700Schasinglulu ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] 85*91f16700Schasinglulu msr elr_el2, x0 86*91f16700Schasinglulu msr spsr_el2, x1 87*91f16700Schasinglulu 88*91f16700Schasinglulu ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] 89*91f16700Schasinglulu ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] 90*91f16700Schasinglulu ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] 91*91f16700Schasinglulu ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] 92*91f16700Schasinglulu exception_return 93*91f16700Schasingluluendfunc bl1_run_next_image 94