1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef FCONF_HW_CONFIG_GETTER_H 8*91f16700Schasinglulu #define FCONF_HW_CONFIG_GETTER_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/fconf/fconf.h> 11*91f16700Schasinglulu #include <services/rmm_core_manifest.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <plat/arm/common/arm_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Hardware Config related getter */ 16*91f16700Schasinglulu #define hw_config__gicv3_config_getter(prop) gicv3_config.prop 17*91f16700Schasinglulu #define hw_config__topology_getter(prop) soc_topology.prop 18*91f16700Schasinglulu #define hw_config__uart_serial_config_getter(prop) uart_serial_config.prop 19*91f16700Schasinglulu #define hw_config__cpu_timer_getter(prop) cpu_timer.prop 20*91f16700Schasinglulu #define hw_config__dram_layout_getter(prop) dram_layout.prop 21*91f16700Schasinglulu 22*91f16700Schasinglulu struct gicv3_config_t { 23*91f16700Schasinglulu uint64_t gicd_base; 24*91f16700Schasinglulu uint64_t gicr_base; 25*91f16700Schasinglulu }; 26*91f16700Schasinglulu 27*91f16700Schasinglulu struct hw_topology_t { 28*91f16700Schasinglulu uint32_t plat_cluster_count; 29*91f16700Schasinglulu uint32_t cluster_cpu_count; 30*91f16700Schasinglulu uint32_t plat_cpu_count; 31*91f16700Schasinglulu uint32_t plat_max_pwr_level; 32*91f16700Schasinglulu }; 33*91f16700Schasinglulu 34*91f16700Schasinglulu struct uart_serial_config_t { 35*91f16700Schasinglulu uint64_t uart_base; 36*91f16700Schasinglulu uint32_t uart_clk; 37*91f16700Schasinglulu }; 38*91f16700Schasinglulu 39*91f16700Schasinglulu struct cpu_timer_t { 40*91f16700Schasinglulu uint32_t clock_freq; 41*91f16700Schasinglulu }; 42*91f16700Schasinglulu 43*91f16700Schasinglulu struct ns_dram_layout { 44*91f16700Schasinglulu uint64_t num_banks; 45*91f16700Schasinglulu struct ns_dram_bank dram_bank[ARM_DRAM_NUM_BANKS]; 46*91f16700Schasinglulu }; 47*91f16700Schasinglulu 48*91f16700Schasinglulu int fconf_populate_gicv3_config(uintptr_t config); 49*91f16700Schasinglulu int fconf_populate_topology(uintptr_t config); 50*91f16700Schasinglulu int fconf_populate_uart_config(uintptr_t config); 51*91f16700Schasinglulu int fconf_populate_cpu_timer(uintptr_t config); 52*91f16700Schasinglulu int fconf_populate_dram_layout(uintptr_t config); 53*91f16700Schasinglulu 54*91f16700Schasinglulu extern struct gicv3_config_t gicv3_config; 55*91f16700Schasinglulu extern struct hw_topology_t soc_topology; 56*91f16700Schasinglulu extern struct uart_serial_config_t uart_serial_config; 57*91f16700Schasinglulu extern struct cpu_timer_t cpu_timer; 58*91f16700Schasinglulu extern struct ns_dram_layout dram_layout; 59*91f16700Schasinglulu 60*91f16700Schasinglulu #endif /* FCONF_HW_CONFIG_GETTER_H */ 61