xref: /arm-trusted-firmware/plat/arm/board/fvp/fvp_drtm_addr.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2022 Arm Limited. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier:    BSD-3-Clause
5*91f16700Schasinglulu  *
6*91f16700Schasinglulu  */
7*91f16700Schasinglulu 
8*91f16700Schasinglulu #include <stdint.h>
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <plat/common/platform.h>
11*91f16700Schasinglulu #include <platform_def.h>
12*91f16700Schasinglulu 
13*91f16700Schasinglulu /*******************************************************************************
14*91f16700Schasinglulu  * Check passed region is within Non-Secure region of DRAM
15*91f16700Schasinglulu  ******************************************************************************/
16*91f16700Schasinglulu int plat_drtm_validate_ns_region(uintptr_t region_start,
17*91f16700Schasinglulu 				 size_t region_size)
18*91f16700Schasinglulu {
19*91f16700Schasinglulu 	uintptr_t region_end = region_start + region_size - 1;
20*91f16700Schasinglulu 
21*91f16700Schasinglulu 	if (region_start >= region_end) {
22*91f16700Schasinglulu 		return -1;
23*91f16700Schasinglulu 	} else if ((region_start >= ARM_NS_DRAM1_BASE) &&
24*91f16700Schasinglulu 		   (region_start < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE)) &&
25*91f16700Schasinglulu 		   (region_end >= ARM_NS_DRAM1_BASE) &&
26*91f16700Schasinglulu 		   (region_end < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
27*91f16700Schasinglulu 		return 0;
28*91f16700Schasinglulu 	} else if ((region_start >= ARM_DRAM2_BASE) &&
29*91f16700Schasinglulu 		   (region_start < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE)) &&
30*91f16700Schasinglulu 		   (region_end >= ARM_DRAM2_BASE) &&
31*91f16700Schasinglulu 		   (region_end < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
32*91f16700Schasinglulu 		return 0;
33*91f16700Schasinglulu 	}
34*91f16700Schasinglulu 
35*91f16700Schasinglulu 	return -1;
36*91f16700Schasinglulu }
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