1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include "fvp_private.h" 10*91f16700Schasinglulu 11*91f16700Schasinglulu void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 12*91f16700Schasinglulu u_register_t arg1 __unused, 13*91f16700Schasinglulu u_register_t arg2 __unused, 14*91f16700Schasinglulu u_register_t arg3 __unused) 15*91f16700Schasinglulu { 16*91f16700Schasinglulu arm_bl2_el3_early_platform_setup(); 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* Initialize the platform config for future decision making */ 19*91f16700Schasinglulu fvp_config_setup(); 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* 22*91f16700Schasinglulu * Initialize Interconnect for this cluster during cold boot. 23*91f16700Schasinglulu * No need for locks as no other CPU is active. 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu fvp_interconnect_init(); 26*91f16700Schasinglulu /* 27*91f16700Schasinglulu * Enable coherency in Interconnect for the primary CPU's cluster. 28*91f16700Schasinglulu */ 29*91f16700Schasinglulu fvp_interconnect_enable(); 30*91f16700Schasinglulu } 31