1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <errno.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <bl1/bl1.h> 11*91f16700Schasinglulu #include <common/tbbr/tbbr_img_def.h> 12*91f16700Schasinglulu #include <drivers/arm/smmu_v3.h> 13*91f16700Schasinglulu #include <drivers/arm/sp805.h> 14*91f16700Schasinglulu #include <lib/mmio.h> 15*91f16700Schasinglulu #include <plat/arm/common/arm_config.h> 16*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 17*91f16700Schasinglulu #include <plat/arm/common/arm_def.h> 18*91f16700Schasinglulu #include <plat/common/platform.h> 19*91f16700Schasinglulu #include "fvp_private.h" 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * Perform any BL1 specific platform actions. 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu void bl1_early_platform_setup(void) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu arm_bl1_early_platform_setup(); 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* Initialize the platform config for future decision making */ 29*91f16700Schasinglulu fvp_config_setup(); 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* 32*91f16700Schasinglulu * Initialize Interconnect for this cluster during cold boot. 33*91f16700Schasinglulu * No need for locks as no other CPU is active. 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu fvp_interconnect_init(); 36*91f16700Schasinglulu /* 37*91f16700Schasinglulu * Enable coherency in Interconnect for the primary CPU's cluster. 38*91f16700Schasinglulu */ 39*91f16700Schasinglulu fvp_interconnect_enable(); 40*91f16700Schasinglulu } 41*91f16700Schasinglulu 42*91f16700Schasinglulu void plat_arm_secure_wdt_start(void) 43*91f16700Schasinglulu { 44*91f16700Schasinglulu sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 45*91f16700Schasinglulu } 46*91f16700Schasinglulu 47*91f16700Schasinglulu void plat_arm_secure_wdt_stop(void) 48*91f16700Schasinglulu { 49*91f16700Schasinglulu sp805_stop(ARM_SP805_TWDG_BASE); 50*91f16700Schasinglulu } 51*91f16700Schasinglulu 52*91f16700Schasinglulu void bl1_platform_setup(void) 53*91f16700Schasinglulu { 54*91f16700Schasinglulu arm_bl1_platform_setup(); 55*91f16700Schasinglulu 56*91f16700Schasinglulu /* Initialize System level generic or SP804 timer */ 57*91f16700Schasinglulu fvp_timer_init(); 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* On FVP RevC, initialize SMMUv3 */ 60*91f16700Schasinglulu if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) 61*91f16700Schasinglulu smmuv3_security_init(PLAT_FVP_SMMUV3_BASE); 62*91f16700Schasinglulu } 63*91f16700Schasinglulu 64*91f16700Schasinglulu __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved) 65*91f16700Schasinglulu { 66*91f16700Schasinglulu uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR); 67*91f16700Schasinglulu 68*91f16700Schasinglulu /* Clear the NV flags register. */ 69*91f16700Schasinglulu mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR), 70*91f16700Schasinglulu nv_flags); 71*91f16700Schasinglulu 72*91f16700Schasinglulu /* Setup the watchdog to reset the system as soon as possible */ 73*91f16700Schasinglulu sp805_refresh(ARM_SP805_TWDG_BASE, 1U); 74*91f16700Schasinglulu 75*91f16700Schasinglulu while (true) 76*91f16700Schasinglulu wfi(); 77*91f16700Schasinglulu } 78*91f16700Schasinglulu 79*91f16700Schasinglulu /******************************************************************************* 80*91f16700Schasinglulu * The following function checks if Firmware update is needed by checking error 81*91f16700Schasinglulu * reported in NV flag. 82*91f16700Schasinglulu ******************************************************************************/ 83*91f16700Schasinglulu bool plat_arm_bl1_fwu_needed(void) 84*91f16700Schasinglulu { 85*91f16700Schasinglulu int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR); 86*91f16700Schasinglulu 87*91f16700Schasinglulu /* if image load/authentication failed */ 88*91f16700Schasinglulu return ((nv_flags == -EAUTH) || (nv_flags == -ENOENT)); 89*91f16700Schasinglulu } 90