1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu/dts-v1/; 7*91f16700Schasinglulu 8*91f16700Schasinglulu#define AFF 00 9*91f16700Schasinglulu 10*91f16700Schasinglulu#include "fvp-defs.dtsi" 11*91f16700Schasinglulu#undef POST 12*91f16700Schasinglulu#define POST \ 13*91f16700Schasinglulu }; 14*91f16700Schasinglulu 15*91f16700Schasinglulu/ { 16*91f16700Schasinglulu compatible = "arm,ffa-core-manifest-1.0"; 17*91f16700Schasinglulu #address-cells = <2>; 18*91f16700Schasinglulu #size-cells = <1>; 19*91f16700Schasinglulu 20*91f16700Schasinglulu attribute { 21*91f16700Schasinglulu spmc_id = <0x8000>; 22*91f16700Schasinglulu maj_ver = <0x1>; 23*91f16700Schasinglulu min_ver = <0x1>; 24*91f16700Schasinglulu exec_state = <0x0>; 25*91f16700Schasinglulu load_address = <0x0 0x6000000>; 26*91f16700Schasinglulu entrypoint = <0x0 0x6000000>; 27*91f16700Schasinglulu binary_size = <0x80000>; 28*91f16700Schasinglulu }; 29*91f16700Schasinglulu 30*91f16700Schasinglulu hypervisor { 31*91f16700Schasinglulu compatible = "hafnium,hafnium"; 32*91f16700Schasinglulu vm1 { 33*91f16700Schasinglulu is_ffa_partition; 34*91f16700Schasinglulu debug_name = "op-tee"; 35*91f16700Schasinglulu load_address = <0x6280000>; 36*91f16700Schasinglulu vcpu_count = <8>; 37*91f16700Schasinglulu mem_size = <1048576>; 38*91f16700Schasinglulu }; 39*91f16700Schasinglulu }; 40*91f16700Schasinglulu 41*91f16700Schasinglulu cpus { 42*91f16700Schasinglulu #address-cells = <0x2>; 43*91f16700Schasinglulu #size-cells = <0x0>; 44*91f16700Schasinglulu 45*91f16700Schasinglulu CPU_0 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* 48*91f16700Schasinglulu * SPMC (Hafnium) requires secondary core nodes are declared 49*91f16700Schasinglulu * in descending order. 50*91f16700Schasinglulu */ 51*91f16700Schasinglulu CPU_7 52*91f16700Schasinglulu CPU_6 53*91f16700Schasinglulu CPU_5 54*91f16700Schasinglulu CPU_4 55*91f16700Schasinglulu CPU_3 56*91f16700Schasinglulu CPU_2 57*91f16700Schasinglulu CPU_1 58*91f16700Schasinglulu }; 59*91f16700Schasinglulu 60*91f16700Schasinglulu memory@6000000 { 61*91f16700Schasinglulu device_type = "memory"; 62*91f16700Schasinglulu reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */ 63*91f16700Schasinglulu }; 64*91f16700Schasinglulu}; 65