1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2020, ARM Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu * The Arm Ltd. FPGA images start execution at address 0x0, which is 7*91f16700Schasinglulu * mapped at an (emulated) ROM image. The payload uploader can write to 8*91f16700Schasinglulu * this memory, but write access by the CPU cores is prohibited. 9*91f16700Schasinglulu * 10*91f16700Schasinglulu * Provide a simple trampoline to start BL31 execution at the actual 11*91f16700Schasinglulu * load address. We put the DTB address in x0, so any code in DRAM could 12*91f16700Schasinglulu * make use of that information (not yet used in BL31 right now). 13*91f16700Schasinglulu */ 14*91f16700Schasinglulu 15*91f16700Schasinglulu#include <asm_macros.S> 16*91f16700Schasinglulu#include <common/bl_common.ld.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu.text 19*91f16700Schasinglulu.global _start 20*91f16700Schasinglulu 21*91f16700Schasinglulu_start: 22*91f16700Schasinglulu mov_imm x1, BL31_BASE /* beginning of DRAM */ 23*91f16700Schasinglulu mov_imm x0, FPGA_PRELOADED_DTB_BASE 24*91f16700Schasinglulu br x1 25