xref: /arm-trusted-firmware/plat/arm/board/arm_fpga/kernel_trampoline.S (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu/*
2*91f16700Schasinglulu * Copyright (c) 2021, ARM Limited. All rights reserved.
3*91f16700Schasinglulu *
4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu *
6*91f16700Schasinglulu * The traditional arm64 Linux kernel load address is 512KiB from the
7*91f16700Schasinglulu * beginning of DRAM, caused by this having been the default value of the
8*91f16700Schasinglulu * kernel's CONFIG_TEXT_OFFSET Kconfig value.
9*91f16700Schasinglulu * However kernel version 5.8 changed the default offset (into a 2MB page)
10*91f16700Schasinglulu * to 0, so TF-A's default assumption is no longer true. Fortunately the
11*91f16700Schasinglulu * kernel got more relaxed about this offset at the same time, so it
12*91f16700Schasinglulu * tolerates the wrong offset, but issues a warning:
13*91f16700Schasinglulu * [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
14*91f16700Schasinglulu *
15*91f16700Schasinglulu * We cannot easily change the load address offset in TF-A to be 2MiB, because
16*91f16700Schasinglulu * this would break older kernels - and they are not as forgiving in this
17*91f16700Schasinglulu * respect.
18*91f16700Schasinglulu *
19*91f16700Schasinglulu * But we can allow users to load the kernel at the right offset, and
20*91f16700Schasinglulu * offer this trampoline here to transition to this new load address.
21*91f16700Schasinglulu * Any older kernels, or newer kernels misloaded, will overwrite this code
22*91f16700Schasinglulu * here, so it does no harm in this case.
23*91f16700Schasinglulu */
24*91f16700Schasinglulu
25*91f16700Schasinglulu#include <asm_macros.S>
26*91f16700Schasinglulu#include <common/bl_common.ld.h>
27*91f16700Schasinglulu
28*91f16700Schasinglulu.text
29*91f16700Schasinglulu.global _tramp_start
30*91f16700Schasinglulu
31*91f16700Schasinglulu_tramp_start:
32*91f16700Schasinglulu	adr	x4, _tramp_start
33*91f16700Schasinglulu	orr	x4, x4, #0x1fffff
34*91f16700Schasinglulu	add	x4, x4, #1			/* align up to 2MB */
35*91f16700Schasinglulu	br	x4
36