1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu #include <plat/common/common_def.h> 12*91f16700Schasinglulu #include <platform_def.h> 13*91f16700Schasinglulu #include "../fpga_def.h" 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define PLATFORM_LINKER_ARCH aarch64 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define PLATFORM_STACK_SIZE UL(0x800) 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define CACHE_WRITEBACK_SHIFT U(6) 22*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define PLATFORM_CORE_COUNT \ 25*91f16700Schasinglulu (FPGA_MAX_CLUSTER_COUNT * \ 26*91f16700Schasinglulu FPGA_MAX_CPUS_PER_CLUSTER * \ 27*91f16700Schasinglulu FPGA_MAX_PE_PER_CPU) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + PLATFORM_CORE_COUNT + 1) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #if !ENABLE_PIE 32*91f16700Schasinglulu #define BL31_BASE UL(0x80000000) 33*91f16700Schasinglulu #define BL31_LIMIT UL(0x80070000) 34*91f16700Schasinglulu #else 35*91f16700Schasinglulu #define BL31_BASE UL(0x0) 36*91f16700Schasinglulu #define BL31_LIMIT UL(0x01000000) 37*91f16700Schasinglulu #endif 38*91f16700Schasinglulu 39*91f16700Schasinglulu #define PLAT_SDEI_NORMAL_PRI 0x70 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define ARM_IRQ_SEC_PHY_TIMER 29 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_0 8 44*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_1 9 45*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_2 10 46*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_3 11 47*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_4 12 48*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_5 13 49*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_6 14 50*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_7 15 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* 53*91f16700Schasinglulu * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 54*91f16700Schasinglulu * terminology. On a GICv2 system or mode, the lists will be merged and treated 55*91f16700Schasinglulu * as Group 0 interrupts. 56*91f16700Schasinglulu */ 57*91f16700Schasinglulu #define PLATFORM_G1S_PROPS(grp) \ 58*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 59*91f16700Schasinglulu GIC_INTR_CFG_LEVEL), \ 60*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 61*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 62*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 63*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 64*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 65*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 66*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 67*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 68*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 69*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 70*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 71*91f16700Schasinglulu GIC_INTR_CFG_EDGE) 72*91f16700Schasinglulu 73*91f16700Schasinglulu #define PLATFORM_G0_PROPS(grp) \ 74*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 75*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 76*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 77*91f16700Schasinglulu GIC_INTR_CFG_EDGE) 78*91f16700Schasinglulu 79*91f16700Schasinglulu #define PLAT_MAX_RET_STATE 1 80*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE 2 81*91f16700Schasinglulu 82*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 83*91f16700Schasinglulu 84*91f16700Schasinglulu #define PLAT_FPGA_HOLD_ENTRY_SHIFT 3 85*91f16700Schasinglulu #define PLAT_FPGA_HOLD_STATE_WAIT 0 86*91f16700Schasinglulu #define PLAT_FPGA_HOLD_STATE_GO 1 87*91f16700Schasinglulu 88*91f16700Schasinglulu #endif 89