1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch_helpers.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <lib/spinlock.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include "fpga_private.h" 12*91f16700Schasinglulu #include <plat/common/platform.h> 13*91f16700Schasinglulu #include <platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2]; 16*91f16700Schasinglulu unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT]; 17*91f16700Schasinglulu 18*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 19*91f16700Schasinglulu { 20*91f16700Schasinglulu unsigned int i; 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* 23*91f16700Schasinglulu * The highest level is the system level. The next level is constituted 24*91f16700Schasinglulu * by clusters and then cores in clusters. 25*91f16700Schasinglulu * 26*91f16700Schasinglulu * This description of the power domain topology is aligned with the CPU 27*91f16700Schasinglulu * indices returned by the plat_core_pos_by_mpidr() and plat_my_core_pos() 28*91f16700Schasinglulu * APIs. 29*91f16700Schasinglulu * 30*91f16700Schasinglulu * A description of the topology tree can be found at 31*91f16700Schasinglulu * https://trustedfirmware-a.readthedocs.io/en/latest/design/psci-pd-tree.html#design 32*91f16700Schasinglulu */ 33*91f16700Schasinglulu 34*91f16700Schasinglulu if (fpga_power_domain_tree_desc[0] == 0U) { 35*91f16700Schasinglulu /* 36*91f16700Schasinglulu * As fpga_power_domain_tree_desc[0] == 0, assume that the 37*91f16700Schasinglulu * Power Domain Topology Tree has not been initialized, so 38*91f16700Schasinglulu * perform the initialization here. 39*91f16700Schasinglulu */ 40*91f16700Schasinglulu 41*91f16700Schasinglulu fpga_power_domain_tree_desc[0] = 1U; 42*91f16700Schasinglulu fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT; 43*91f16700Schasinglulu 44*91f16700Schasinglulu for (i = 0U; i < FPGA_MAX_CLUSTER_COUNT; i++) { 45*91f16700Schasinglulu fpga_power_domain_tree_desc[2 + i] = 46*91f16700Schasinglulu (FPGA_MAX_CPUS_PER_CLUSTER * 47*91f16700Schasinglulu FPGA_MAX_PE_PER_CPU); 48*91f16700Schasinglulu } 49*91f16700Schasinglulu } 50*91f16700Schasinglulu 51*91f16700Schasinglulu return fpga_power_domain_tree_desc; 52*91f16700Schasinglulu } 53*91f16700Schasinglulu 54*91f16700Schasinglulu int plat_core_pos_by_mpidr(u_register_t mpidr) 55*91f16700Schasinglulu { 56*91f16700Schasinglulu unsigned int core_pos; 57*91f16700Schasinglulu 58*91f16700Schasinglulu mpidr &= (MPID_MASK & ~(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); 59*91f16700Schasinglulu mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 60*91f16700Schasinglulu 61*91f16700Schasinglulu if ((MPIDR_AFFLVL2_VAL(mpidr) >= FPGA_MAX_CLUSTER_COUNT) || 62*91f16700Schasinglulu (MPIDR_AFFLVL1_VAL(mpidr) >= FPGA_MAX_CPUS_PER_CLUSTER) || 63*91f16700Schasinglulu (MPIDR_AFFLVL0_VAL(mpidr) >= FPGA_MAX_PE_PER_CPU)) { 64*91f16700Schasinglulu ERROR ("Invalid mpidr: 0x%08x\n", (uint32_t)mpidr); 65*91f16700Schasinglulu panic(); 66*91f16700Schasinglulu } 67*91f16700Schasinglulu 68*91f16700Schasinglulu /* Calculate the core position, based on the maximum topology. */ 69*91f16700Schasinglulu core_pos = plat_fpga_calc_core_pos(mpidr); 70*91f16700Schasinglulu 71*91f16700Schasinglulu /* Check whether this core is actually present. */ 72*91f16700Schasinglulu if (fpga_valid_mpids[core_pos] != VALID_MPID) { 73*91f16700Schasinglulu return -1; 74*91f16700Schasinglulu } 75*91f16700Schasinglulu 76*91f16700Schasinglulu return core_pos; 77*91f16700Schasinglulu } 78