1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2020, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu #include <plat/arm/common/arm_config.h> 13*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define MAP_PERIPHBASE MAP_REGION_FLAT(PERIPHBASE,\ 16*91f16700Schasinglulu PERIPH_SIZE,\ 17*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define MAP_A5_PERIPHERALS MAP_REGION_FLAT(A5_PERIPHERALS_BASE,\ 20*91f16700Schasinglulu A5_PERIPHERALS_SIZE,\ 21*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #ifdef IMAGE_BL1 24*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 25*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 26*91f16700Schasinglulu MAP_PERIPHBASE, 27*91f16700Schasinglulu MAP_A5_PERIPHERALS, 28*91f16700Schasinglulu MAP_BOOT_RW, 29*91f16700Schasinglulu {0} 30*91f16700Schasinglulu }; 31*91f16700Schasinglulu #endif 32*91f16700Schasinglulu #ifdef IMAGE_BL2 33*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 34*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 35*91f16700Schasinglulu MAP_PERIPHBASE, 36*91f16700Schasinglulu MAP_A5_PERIPHERALS, 37*91f16700Schasinglulu MAP_BOOT_RW, 38*91f16700Schasinglulu ARM_MAP_NS_DRAM1, 39*91f16700Schasinglulu {0} 40*91f16700Schasinglulu }; 41*91f16700Schasinglulu #endif 42*91f16700Schasinglulu #ifdef IMAGE_BL32 43*91f16700Schasinglulu const mmap_region_t plat_arm_mmap[] = { 44*91f16700Schasinglulu ARM_MAP_SHARED_RAM, 45*91f16700Schasinglulu MAP_PERIPHBASE, 46*91f16700Schasinglulu MAP_A5_PERIPHERALS, 47*91f16700Schasinglulu {0} 48*91f16700Schasinglulu }; 49*91f16700Schasinglulu #endif 50*91f16700Schasinglulu 51*91f16700Schasinglulu ARM_CASSERT_MMAP 52*91f16700Schasinglulu 53*91f16700Schasinglulu unsigned int plat_get_syscnt_freq2(void) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu return A5DS_TIMER_BASE_FREQUENCY; 56*91f16700Schasinglulu } 57