1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu 7*91f16700Schasingluluinclude lib/xlat_tables_v2/xlat_tables.mk 8*91f16700Schasinglulu 9*91f16700SchasingluluAML_PLAT := plat/amlogic 10*91f16700SchasingluluAML_PLAT_SOC := ${AML_PLAT}/${PLAT} 11*91f16700SchasingluluAML_PLAT_COMMON := ${AML_PLAT}/common 12*91f16700Schasinglulu 13*91f16700SchasingluluPLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ 14*91f16700Schasinglulu -I${AML_PLAT_SOC}/include \ 15*91f16700Schasinglulu -I${AML_PLAT_COMMON}/include 16*91f16700Schasinglulu 17*91f16700SchasingluluGIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 18*91f16700Schasinglulu drivers/arm/gic/v2/gicv2_main.c \ 19*91f16700Schasinglulu drivers/arm/gic/v2/gicv2_helpers.c \ 20*91f16700Schasinglulu plat/common/plat_gicv2.c 21*91f16700Schasinglulu 22*91f16700SchasingluluBL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 23*91f16700Schasinglulu plat/common/plat_psci_common.c \ 24*91f16700Schasinglulu drivers/amlogic/console/aarch64/meson_console.S \ 25*91f16700Schasinglulu ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \ 26*91f16700Schasinglulu ${AML_PLAT_SOC}/${PLAT}_pm.c \ 27*91f16700Schasinglulu ${AML_PLAT_SOC}/${PLAT}_common.c \ 28*91f16700Schasinglulu ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ 29*91f16700Schasinglulu ${AML_PLAT_COMMON}/aml_efuse.c \ 30*91f16700Schasinglulu ${AML_PLAT_COMMON}/aml_mhu.c \ 31*91f16700Schasinglulu ${AML_PLAT_COMMON}/aml_scpi.c \ 32*91f16700Schasinglulu ${AML_PLAT_COMMON}/aml_sip_svc.c \ 33*91f16700Schasinglulu ${AML_PLAT_COMMON}/aml_thermal.c \ 34*91f16700Schasinglulu ${AML_PLAT_COMMON}/aml_topology.c \ 35*91f16700Schasinglulu ${AML_PLAT_COMMON}/aml_console.c \ 36*91f16700Schasinglulu ${XLAT_TABLES_LIB_SRCS} \ 37*91f16700Schasinglulu ${GIC_SOURCES} 38*91f16700Schasinglulu 39*91f16700Schasinglulu# Tune compiler for Cortex-A53 40*91f16700Schasingluluifeq ($(notdir $(CC)),armclang) 41*91f16700Schasinglulu TF_CFLAGS_aarch64 += -mcpu=cortex-a53 42*91f16700Schasingluluelse ifneq ($(findstring clang,$(notdir $(CC))),) 43*91f16700Schasinglulu TF_CFLAGS_aarch64 += -mcpu=cortex-a53 44*91f16700Schasingluluelse 45*91f16700Schasinglulu TF_CFLAGS_aarch64 += -mtune=cortex-a53 46*91f16700Schasingluluendif 47*91f16700Schasinglulu 48*91f16700Schasinglulu# Build config flags 49*91f16700Schasinglulu# ------------------ 50*91f16700Schasinglulu 51*91f16700Schasinglulu# Enable all errata workarounds for Cortex-A53 52*91f16700SchasingluluERRATA_A53_826319 := 1 53*91f16700SchasingluluERRATA_A53_835769 := 1 54*91f16700SchasingluluERRATA_A53_836870 := 1 55*91f16700SchasingluluERRATA_A53_843419 := 1 56*91f16700SchasingluluERRATA_A53_855873 := 1 57*91f16700Schasinglulu 58*91f16700SchasingluluWORKAROUND_CVE_2017_5715 := 0 59*91f16700Schasinglulu 60*91f16700Schasinglulu# Have different sections for code and rodata 61*91f16700SchasingluluSEPARATE_CODE_AND_RODATA := 1 62*91f16700Schasinglulu 63*91f16700Schasinglulu# Use Coherent memory 64*91f16700SchasingluluUSE_COHERENT_MEM := 1 65*91f16700Schasinglulu 66*91f16700Schasinglulu# Verify build config 67*91f16700Schasinglulu# ------------------- 68*91f16700Schasinglulu 69*91f16700Schasingluluifneq (${RESET_TO_BL31}, 0) 70*91f16700Schasinglulu $(error Error: ${PLAT} needs RESET_TO_BL31=0) 71*91f16700Schasingluluendif 72*91f16700Schasinglulu 73*91f16700Schasingluluifeq (${ARCH},aarch32) 74*91f16700Schasinglulu $(error Error: AArch32 not supported on ${PLAT}) 75*91f16700Schasingluluendif 76