1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu #include <lib/utils_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include "../gxbb_def.h" 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 16*91f16700Schasinglulu #define PLATFORM_LINKER_ARCH aarch64 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* Special value used to verify platform parameters from BL2 to BL31 */ 19*91f16700Schasinglulu #define AML_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978) 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define PLATFORM_STACK_SIZE UL(0x1000) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 24*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT U(1) 25*91f16700Schasinglulu #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 26*91f16700Schasinglulu #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define AML_PRIMARY_CPU U(0) 29*91f16700Schasinglulu 30*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 31*91f16700Schasinglulu #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 32*91f16700Schasinglulu PLATFORM_CORE_COUNT) 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define PLAT_MAX_RET_STATE U(1) 35*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE U(2) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* Local power state for power domains in Run state. */ 38*91f16700Schasinglulu #define PLAT_LOCAL_STATE_RUN U(0) 39*91f16700Schasinglulu /* Local power state for retention. Valid only for CPU power domains */ 40*91f16700Schasinglulu #define PLAT_LOCAL_STATE_RET U(1) 41*91f16700Schasinglulu /* Local power state for power-down. Valid for CPU and cluster power domains. */ 42*91f16700Schasinglulu #define PLAT_LOCAL_STATE_OFF U(2) 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* 45*91f16700Schasinglulu * Macros used to parse state information from State-ID if it is using the 46*91f16700Schasinglulu * recommended encoding for State-ID. 47*91f16700Schasinglulu */ 48*91f16700Schasinglulu #define PLAT_LOCAL_PSTATE_WIDTH U(4) 49*91f16700Schasinglulu #define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1) 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* 52*91f16700Schasinglulu * Some data must be aligned on the biggest cache line size in the platform. 53*91f16700Schasinglulu * This is known only to the platform as it might have a combination of 54*91f16700Schasinglulu * integrated and external caches. 55*91f16700Schasinglulu */ 56*91f16700Schasinglulu #define CACHE_WRITEBACK_SHIFT U(6) 57*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* Memory-related defines */ 60*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 61*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 62*91f16700Schasinglulu 63*91f16700Schasinglulu #define MAX_MMAP_REGIONS 12 64*91f16700Schasinglulu #define MAX_XLAT_TABLES 5 65*91f16700Schasinglulu 66*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 67