1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#ifndef PLAT_MACROS_S 8*91f16700Schasinglulu#define PLAT_MACROS_S 9*91f16700Schasinglulu 10*91f16700Schasinglulu#include <drivers/arm/gicv2.h> 11*91f16700Schasinglulu#include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu.section .rodata.gic_reg_name, "aS" 14*91f16700Schasinglulu 15*91f16700Schasinglulugicc_regs: 16*91f16700Schasinglulu .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 17*91f16700Schasinglulugicd_pend_reg: 18*91f16700Schasinglulu .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 19*91f16700Schasinglulunewline: 20*91f16700Schasinglulu .asciz "\n" 21*91f16700Schasingluluspacer: 22*91f16700Schasinglulu .asciz ":\t\t0x" 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* --------------------------------------------- 25*91f16700Schasinglulu * The below required platform porting macro 26*91f16700Schasinglulu * prints out relevant GIC and CCI registers 27*91f16700Schasinglulu * whenever an unhandled exception is taken in 28*91f16700Schasinglulu * BL31. 29*91f16700Schasinglulu * Clobbers: x0 - x10, x16, x17, sp 30*91f16700Schasinglulu * --------------------------------------------- 31*91f16700Schasinglulu */ 32*91f16700Schasinglulu .macro plat_crash_print_regs 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* GICC registers */ 35*91f16700Schasinglulu 36*91f16700Schasinglulu mov_imm x17, AML_GICC_BASE 37*91f16700Schasinglulu 38*91f16700Schasinglulu adr x6, gicc_regs 39*91f16700Schasinglulu ldr w8, [x17, #GICC_HPPIR] 40*91f16700Schasinglulu ldr w9, [x17, #GICC_AHPPIR] 41*91f16700Schasinglulu ldr w10, [x17, #GICC_CTLR] 42*91f16700Schasinglulu bl str_in_crash_buf_print 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* GICD registers */ 45*91f16700Schasinglulu 46*91f16700Schasinglulu mov_imm x16, AML_GICD_BASE 47*91f16700Schasinglulu 48*91f16700Schasinglulu add x7, x16, #GICD_ISPENDR 49*91f16700Schasinglulu adr x4, gicd_pend_reg 50*91f16700Schasinglulu bl asm_print_str 51*91f16700Schasinglulu 52*91f16700Schasinglulugicd_ispendr_loop: 53*91f16700Schasinglulu sub x4, x7, x16 54*91f16700Schasinglulu cmp x4, #0x280 55*91f16700Schasinglulu b.eq exit_print_gic_regs 56*91f16700Schasinglulu bl asm_print_hex 57*91f16700Schasinglulu 58*91f16700Schasinglulu adr x4, spacer 59*91f16700Schasinglulu bl asm_print_str 60*91f16700Schasinglulu 61*91f16700Schasinglulu ldr x4, [x7], #8 62*91f16700Schasinglulu bl asm_print_hex 63*91f16700Schasinglulu 64*91f16700Schasinglulu adr x4, newline 65*91f16700Schasinglulu bl asm_print_str 66*91f16700Schasinglulu b gicd_ispendr_loop 67*91f16700Schasingluluexit_print_gic_regs: 68*91f16700Schasinglulu 69*91f16700Schasinglulu .endm 70*91f16700Schasinglulu 71*91f16700Schasinglulu#endif /* PLAT_MACROS_S */ 72