1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SUNXI_MMAP_H 8*91f16700Schasinglulu #define SUNXI_MMAP_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Memory regions */ 11*91f16700Schasinglulu #define SUNXI_ROM_BASE 0x00000000 12*91f16700Schasinglulu #define SUNXI_ROM_SIZE 0x00010000 13*91f16700Schasinglulu /* 14*91f16700Schasinglulu * In fact all SRAM from 0x100000 is SRAM A2. However as it's too big for 15*91f16700Schasinglulu * firmware, and the user manual gives a tip on a 2*64K/27*64K partition, 16*91f16700Schasinglulu * only use the first 2*64K for firmwares now, with the SPL using the first 17*91f16700Schasinglulu * 64K and BL3-1 using the second one. 18*91f16700Schasinglulu * 19*91f16700Schasinglulu * Only the used 2*64K SRAM is defined here, to prevent a gaint translation 20*91f16700Schasinglulu * table to be generated. 21*91f16700Schasinglulu */ 22*91f16700Schasinglulu #define SUNXI_SRAM_BASE 0x00100000 23*91f16700Schasinglulu #define SUNXI_SRAM_SIZE 0x00020000 24*91f16700Schasinglulu #define SUNXI_SRAM_A1_BASE 0x00100000 25*91f16700Schasinglulu #define SUNXI_SRAM_A1_SIZE 0x00010000 26*91f16700Schasinglulu #define SUNXI_SRAM_A2_BASE 0x00110000 27*91f16700Schasinglulu #define SUNXI_SRAM_A2_BL31_OFFSET 0x00000000 28*91f16700Schasinglulu #define SUNXI_SRAM_A2_SIZE 0x00010000 29*91f16700Schasinglulu #define SUNXI_DEV_BASE 0x01000000 30*91f16700Schasinglulu #define SUNXI_DEV_SIZE 0x09000000 31*91f16700Schasinglulu #define SUNXI_DRAM_BASE 0x40000000 32*91f16700Schasinglulu #define SUNXI_DRAM_VIRT_BASE 0x0a000000 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* Memory-mapped devices */ 35*91f16700Schasinglulu #define SUNXI_WDOG_BASE 0x020000a0 36*91f16700Schasinglulu #define SUNXI_R_WDOG_BASE SUNXI_WDOG_BASE 37*91f16700Schasinglulu #define SUNXI_PIO_BASE 0x02000400 38*91f16700Schasinglulu #define SUNXI_SPC_BASE 0x02000800 39*91f16700Schasinglulu #define SUNXI_CCU_BASE 0x02001000 40*91f16700Schasinglulu #define SUNXI_UART0_BASE 0x02500000 41*91f16700Schasinglulu #define SUNXI_SYSCON_BASE 0x03000000 42*91f16700Schasinglulu #define SUNXI_DMA_BASE 0x03002000 43*91f16700Schasinglulu #define SUNXI_SID_BASE 0x03006000 44*91f16700Schasinglulu #define SUNXI_GICD_BASE 0x03021000 45*91f16700Schasinglulu #define SUNXI_GICC_BASE 0x03022000 46*91f16700Schasinglulu #define SUNXI_SPI0_BASE 0x04025000 47*91f16700Schasinglulu #define SUNXI_R_CPUCFG_BASE 0x07000400 48*91f16700Schasinglulu #define SUNXI_R_PRCM_BASE 0x07010000 49*91f16700Schasinglulu #define SUNXI_R_PIO_BASE 0x07022000 50*91f16700Schasinglulu #define SUNXI_R_UART_BASE 0x07080000 51*91f16700Schasinglulu #define SUNXI_R_I2C_BASE 0x07081400 52*91f16700Schasinglulu #define SUNXI_CPUCFG_BASE 0x08100000 53*91f16700Schasinglulu #define SUNXI_C0_CPUXCFG_BASE 0x09010000 54*91f16700Schasinglulu 55*91f16700Schasinglulu #endif /* SUNXI_MMAP_H */ 56