1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SUNXI_MMAP_H 8*91f16700Schasinglulu #define SUNXI_MMAP_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Memory regions */ 11*91f16700Schasinglulu #define SUNXI_ROM_BASE 0x00000000 12*91f16700Schasinglulu #define SUNXI_ROM_SIZE 0x00010000 13*91f16700Schasinglulu #define SUNXI_SRAM_BASE 0x00020000 14*91f16700Schasinglulu #define SUNXI_SRAM_SIZE 0x00038000 15*91f16700Schasinglulu #define SUNXI_SRAM_A1_BASE 0x00020000 16*91f16700Schasinglulu #define SUNXI_SRAM_A1_SIZE 0x00008000 17*91f16700Schasinglulu #define SUNXI_SRAM_C_BASE 0x00028000 18*91f16700Schasinglulu #define SUNXI_SRAM_C_SIZE 0x00030000 19*91f16700Schasinglulu #define SUNXI_DEV_BASE 0x01000000 20*91f16700Schasinglulu #define SUNXI_DEV_SIZE 0x09000000 21*91f16700Schasinglulu #define SUNXI_DRAM_BASE 0x40000000 22*91f16700Schasinglulu #define SUNXI_DRAM_VIRT_BASE SUNXI_DRAM_BASE 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* Memory-mapped devices */ 25*91f16700Schasinglulu #define SUNXI_SYSCON_BASE 0x03000000 26*91f16700Schasinglulu #define SUNXI_CCU_BASE 0x03001000 27*91f16700Schasinglulu #define SUNXI_DMA_BASE 0x03002000 28*91f16700Schasinglulu #define SUNXI_SID_BASE 0x03006000 29*91f16700Schasinglulu #define SUNXI_SPC_BASE 0x03008000 30*91f16700Schasinglulu #define SUNXI_WDOG_BASE 0x030090a0 31*91f16700Schasinglulu #define SUNXI_PIO_BASE 0x0300b000 32*91f16700Schasinglulu #define SUNXI_GICD_BASE 0x03021000 33*91f16700Schasinglulu #define SUNXI_GICC_BASE 0x03022000 34*91f16700Schasinglulu #define SUNXI_UART0_BASE 0x05000000 35*91f16700Schasinglulu #define SUNXI_SPI0_BASE 0x05010000 36*91f16700Schasinglulu #define SUNXI_R_CPUCFG_BASE 0x07000400 37*91f16700Schasinglulu #define SUNXI_R_PRCM_BASE 0x07010000 38*91f16700Schasinglulu //#define SUNXI_R_WDOG_BASE 0x07020400 39*91f16700Schasinglulu #define SUNXI_R_WDOG_BASE SUNXI_WDOG_BASE 40*91f16700Schasinglulu #define SUNXI_R_PIO_BASE 0x07022000 41*91f16700Schasinglulu #define SUNXI_R_UART_BASE 0x07080000 42*91f16700Schasinglulu #define SUNXI_R_I2C_BASE 0x07081400 43*91f16700Schasinglulu #define SUNXI_R_RSB_BASE 0x07083000 44*91f16700Schasinglulu #define SUNXI_CPUSUBSYS_BASE 0x08100000 45*91f16700Schasinglulu #define SUNXI_CPUCFG_BASE 0x09010000 46*91f16700Schasinglulu 47*91f16700Schasinglulu #endif /* SUNXI_MMAP_H */ 48