1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SUNXI_MMAP_H 8*91f16700Schasinglulu #define SUNXI_MMAP_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Memory regions */ 11*91f16700Schasinglulu #define SUNXI_ROM_BASE 0x00000000 12*91f16700Schasinglulu #define SUNXI_ROM_SIZE 0x00010000 13*91f16700Schasinglulu #define SUNXI_SRAM_BASE 0x00020000 14*91f16700Schasinglulu #define SUNXI_SRAM_SIZE 0x000f8000 15*91f16700Schasinglulu #define SUNXI_SRAM_A1_BASE 0x00020000 16*91f16700Schasinglulu #define SUNXI_SRAM_A1_SIZE 0x00008000 17*91f16700Schasinglulu #define SUNXI_SRAM_A2_BASE 0x00100000 18*91f16700Schasinglulu #define SUNXI_SRAM_A2_BL31_OFFSET 0x00004000 19*91f16700Schasinglulu #define SUNXI_SRAM_A2_SIZE 0x00018000 20*91f16700Schasinglulu #define SUNXI_SRAM_C_BASE 0x00028000 21*91f16700Schasinglulu #define SUNXI_SRAM_C_SIZE 0x0001e000 22*91f16700Schasinglulu #define SUNXI_DEV_BASE 0x01000000 23*91f16700Schasinglulu #define SUNXI_DEV_SIZE 0x09000000 24*91f16700Schasinglulu #define SUNXI_DRAM_BASE 0x40000000 25*91f16700Schasinglulu #define SUNXI_DRAM_VIRT_BASE 0x0a000000 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* Memory-mapped devices */ 28*91f16700Schasinglulu #define SUNXI_SYSCON_BASE 0x03000000 29*91f16700Schasinglulu #define SUNXI_CPUCFG_BASE 0x09010000 30*91f16700Schasinglulu #define SUNXI_SID_BASE 0x03006000 31*91f16700Schasinglulu #define SUNXI_DMA_BASE 0x03002000 32*91f16700Schasinglulu #define SUNXI_MSGBOX_BASE 0x03003000 33*91f16700Schasinglulu #define SUNXI_CCU_BASE 0x03001000 34*91f16700Schasinglulu #define SUNXI_PIO_BASE 0x0300b000 35*91f16700Schasinglulu #define SUNXI_SPC_BASE 0x03008000 36*91f16700Schasinglulu #define SUNXI_TIMER_BASE 0x03009000 37*91f16700Schasinglulu #define SUNXI_WDOG_BASE 0x030090a0 38*91f16700Schasinglulu #define SUNXI_THS_BASE 0x05070400 39*91f16700Schasinglulu #define SUNXI_UART0_BASE 0x05000000 40*91f16700Schasinglulu #define SUNXI_UART1_BASE 0x05000400 41*91f16700Schasinglulu #define SUNXI_UART2_BASE 0x05000800 42*91f16700Schasinglulu #define SUNXI_UART3_BASE 0x05000c00 43*91f16700Schasinglulu #define SUNXI_I2C0_BASE 0x05002000 44*91f16700Schasinglulu #define SUNXI_I2C1_BASE 0x05002400 45*91f16700Schasinglulu #define SUNXI_I2C2_BASE 0x05002800 46*91f16700Schasinglulu #define SUNXI_I2C3_BASE 0x05002c00 47*91f16700Schasinglulu #define SUNXI_SPI0_BASE 0x05010000 48*91f16700Schasinglulu #define SUNXI_SPI1_BASE 0x05011000 49*91f16700Schasinglulu #define SUNXI_SCU_BASE 0x03020000 50*91f16700Schasinglulu #define SUNXI_GICD_BASE 0x03021000 51*91f16700Schasinglulu #define SUNXI_GICC_BASE 0x03022000 52*91f16700Schasinglulu #define SUNXI_R_TIMER_BASE 0x07020000 53*91f16700Schasinglulu #define SUNXI_R_INTC_BASE 0x07021000 54*91f16700Schasinglulu #define SUNXI_R_WDOG_BASE 0x07020400 55*91f16700Schasinglulu #define SUNXI_R_PRCM_BASE 0x07010000 56*91f16700Schasinglulu #define SUNXI_R_TWD_BASE 0x07020800 57*91f16700Schasinglulu #define SUNXI_R_CPUCFG_BASE 0x07000400 58*91f16700Schasinglulu #define SUNXI_R_I2C_BASE 0x07081400 59*91f16700Schasinglulu #define SUNXI_R_RSB_BASE 0x07083000 60*91f16700Schasinglulu #define SUNXI_R_UART_BASE 0x07080000 61*91f16700Schasinglulu #define SUNXI_R_PIO_BASE 0x07022000 62*91f16700Schasinglulu #define SUNXI_CPUSUBSYS_BASE 0x08100000 63*91f16700Schasinglulu 64*91f16700Schasinglulu #endif /* SUNXI_MMAP_H */ 65