1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SUNXI_CPUCFG_H 8*91f16700Schasinglulu #define SUNXI_CPUCFG_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <sunxi_mmap.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* c = cluster, n = core */ 13*91f16700Schasinglulu #define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 16) 14*91f16700Schasinglulu #define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0004 + (c) * 16) 15*91f16700Schasinglulu #define SUNXI_CPUCFG_CACHE_CFG_REG0 (SUNXI_CPUCFG_BASE + 0x0008) 16*91f16700Schasinglulu #define SUNXI_CPUCFG_CACHE_CFG_REG1 (SUNXI_CPUCFG_BASE + 0x000c) 17*91f16700Schasinglulu #define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x0020) 18*91f16700Schasinglulu #define SUNXI_CPUCFG_GLB_CTRL_REG (SUNXI_CPUCFG_BASE + 0x0028) 19*91f16700Schasinglulu #define SUNXI_CPUCFG_CPU_STS_REG(c) (SUNXI_CPUCFG_BASE + 0x0030 + (c) * 4) 20*91f16700Schasinglulu #define SUNXI_CPUCFG_L2_STS_REG (SUNXI_CPUCFG_BASE + 0x003c) 21*91f16700Schasinglulu #define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0080 + (c) * 4) 22*91f16700Schasinglulu #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x00a0 + (n) * 8) 23*91f16700Schasinglulu #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x00a4 + (n) * 8) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \ 26*91f16700Schasinglulu (c) * 16 + (n) * 4) 27*91f16700Schasinglulu #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_PRCM_BASE + 0x0100 + (c) * 4) 28*91f16700Schasinglulu #define SUNXI_R_CPUCFG_CPUS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0000) 29*91f16700Schasinglulu #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0030 + (c) * 4) 30*91f16700Schasinglulu #define SUNXI_R_CPUCFG_SYS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0140) 31*91f16700Schasinglulu #define SUNXI_R_CPUCFG_SS_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01a0) 32*91f16700Schasinglulu #define SUNXI_R_CPUCFG_CPU_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a4) 33*91f16700Schasinglulu #define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8) 34*91f16700Schasinglulu #define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac) 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 37*91f16700Schasinglulu #define SUNXI_AA64nAA32_OFFSET 24 38*91f16700Schasinglulu 39*91f16700Schasinglulu static inline bool sunxi_cpucfg_has_per_cluster_regs(void) 40*91f16700Schasinglulu { 41*91f16700Schasinglulu return true; 42*91f16700Schasinglulu } 43*91f16700Schasinglulu 44*91f16700Schasinglulu #endif /* SUNXI_CPUCFG_H */ 45