1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <arch.h> 10*91f16700Schasinglulu #include <plat/common/platform.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu static const unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = { 13*91f16700Schasinglulu /* One root node for the SoC */ 14*91f16700Schasinglulu 1, 15*91f16700Schasinglulu /* One node for each cluster */ 16*91f16700Schasinglulu PLATFORM_CLUSTER_COUNT, 17*91f16700Schasinglulu /* One set of CPUs per cluster */ 18*91f16700Schasinglulu PLATFORM_MAX_CPUS_PER_CLUSTER, 19*91f16700Schasinglulu }; 20*91f16700Schasinglulu 21*91f16700Schasinglulu int plat_core_pos_by_mpidr(u_register_t mpidr) 22*91f16700Schasinglulu { 23*91f16700Schasinglulu unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 24*91f16700Schasinglulu unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 25*91f16700Schasinglulu 26*91f16700Schasinglulu if (MPIDR_AFFLVL3_VAL(mpidr) > 0 || 27*91f16700Schasinglulu MPIDR_AFFLVL2_VAL(mpidr) > 0 || 28*91f16700Schasinglulu cluster >= PLATFORM_CLUSTER_COUNT || 29*91f16700Schasinglulu core >= PLATFORM_MAX_CPUS_PER_CLUSTER) { 30*91f16700Schasinglulu return -1; 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu return cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core; 34*91f16700Schasinglulu } 35*91f16700Schasinglulu 36*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 37*91f16700Schasinglulu { 38*91f16700Schasinglulu return plat_power_domain_tree_desc; 39*91f16700Schasinglulu } 40