1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch_helpers.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <drivers/arm/gicv2.h> 10*91f16700Schasinglulu #include <drivers/delay_timer.h> 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu #include <lib/psci/psci.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <sunxi_mmap.h> 15*91f16700Schasinglulu #include <sunxi_private.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010) 18*91f16700Schasinglulu #define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014) 19*91f16700Schasinglulu #define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018) 20*91f16700Schasinglulu 21*91f16700Schasinglulu static int sunxi_pwr_domain_on(u_register_t mpidr) 22*91f16700Schasinglulu { 23*91f16700Schasinglulu sunxi_cpu_on(mpidr); 24*91f16700Schasinglulu 25*91f16700Schasinglulu return PSCI_E_SUCCESS; 26*91f16700Schasinglulu } 27*91f16700Schasinglulu 28*91f16700Schasinglulu static void sunxi_pwr_domain_off(const psci_power_state_t *target_state) 29*91f16700Schasinglulu { 30*91f16700Schasinglulu gicv2_cpuif_disable(); 31*91f16700Schasinglulu 32*91f16700Schasinglulu sunxi_cpu_power_off_self(); 33*91f16700Schasinglulu } 34*91f16700Schasinglulu 35*91f16700Schasinglulu static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state) 36*91f16700Schasinglulu { 37*91f16700Schasinglulu gicv2_pcpu_distif_init(); 38*91f16700Schasinglulu gicv2_cpuif_enable(); 39*91f16700Schasinglulu } 40*91f16700Schasinglulu 41*91f16700Schasinglulu static void __dead2 sunxi_system_off(void) 42*91f16700Schasinglulu { 43*91f16700Schasinglulu gicv2_cpuif_disable(); 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* Attempt to power down the board (may not return) */ 46*91f16700Schasinglulu sunxi_power_down(); 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* Turn off all CPUs */ 49*91f16700Schasinglulu sunxi_cpu_power_off_others(); 50*91f16700Schasinglulu sunxi_cpu_power_off_self(); 51*91f16700Schasinglulu psci_power_down_wfi(); 52*91f16700Schasinglulu } 53*91f16700Schasinglulu 54*91f16700Schasinglulu static void __dead2 sunxi_system_reset(void) 55*91f16700Schasinglulu { 56*91f16700Schasinglulu gicv2_cpuif_disable(); 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* Reset the whole system when the watchdog times out */ 59*91f16700Schasinglulu mmio_write_32(SUNXI_WDOG0_CFG_REG, 1); 60*91f16700Schasinglulu /* Enable the watchdog with the shortest timeout (0.5 seconds) */ 61*91f16700Schasinglulu mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1); 62*91f16700Schasinglulu /* Wait for twice the watchdog timeout before panicking */ 63*91f16700Schasinglulu mdelay(1000); 64*91f16700Schasinglulu 65*91f16700Schasinglulu ERROR("PSCI: System reset failed\n"); 66*91f16700Schasinglulu panic(); 67*91f16700Schasinglulu } 68*91f16700Schasinglulu 69*91f16700Schasinglulu static const plat_psci_ops_t sunxi_native_psci_ops = { 70*91f16700Schasinglulu .pwr_domain_on = sunxi_pwr_domain_on, 71*91f16700Schasinglulu .pwr_domain_off = sunxi_pwr_domain_off, 72*91f16700Schasinglulu .pwr_domain_on_finish = sunxi_pwr_domain_on_finish, 73*91f16700Schasinglulu .system_off = sunxi_system_off, 74*91f16700Schasinglulu .system_reset = sunxi_system_reset, 75*91f16700Schasinglulu .validate_ns_entrypoint = sunxi_validate_ns_entrypoint, 76*91f16700Schasinglulu }; 77*91f16700Schasinglulu 78*91f16700Schasinglulu void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops) 79*91f16700Schasinglulu { 80*91f16700Schasinglulu *psci_ops = &sunxi_native_psci_ops; 81*91f16700Schasinglulu } 82