1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SUNXI_DEF_H 8*91f16700Schasinglulu #define SUNXI_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Clock configuration */ 11*91f16700Schasinglulu #define SUNXI_OSC24M_CLK_IN_HZ 24000000 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* UART configuration */ 14*91f16700Schasinglulu #define SUNXI_UART0_BAUDRATE 115200 15*91f16700Schasinglulu #define SUNXI_UART0_CLK_IN_HZ SUNXI_OSC24M_CLK_IN_HZ 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define SUNXI_SOC_A64 0x1689 18*91f16700Schasinglulu #define SUNXI_SOC_H5 0x1718 19*91f16700Schasinglulu #define SUNXI_SOC_H6 0x1728 20*91f16700Schasinglulu #define SUNXI_SOC_H616 0x1823 21*91f16700Schasinglulu #define SUNXI_SOC_R329 0x1851 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define SUNXI_VER_BITS_MASK 0xffU 24*91f16700Schasinglulu #define JEDEC_ALLWINNER_BKID 9U 25*91f16700Schasinglulu #define JEDEC_ALLWINNER_MFID 0x9eU 26*91f16700Schasinglulu 27*91f16700Schasinglulu #endif /* SUNXI_DEF_H */ 28