1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <assert_macros.S> 9*91f16700Schasinglulu#include <lib/xlat_tables/xlat_tables_v2.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .global enable_mmu_direct_el1 12*91f16700Schasinglulu .global enable_mmu_direct_el2 13*91f16700Schasinglulu .global enable_mmu_direct_el3 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Macros to read and write to system register for a given EL. */ 16*91f16700Schasinglulu .macro _msr reg_name, el, gp_reg 17*91f16700Schasinglulu msr \reg_name\()_el\()\el, \gp_reg 18*91f16700Schasinglulu .endm 19*91f16700Schasinglulu 20*91f16700Schasinglulu .macro _mrs gp_reg, reg_name, el 21*91f16700Schasinglulu mrs \gp_reg, \reg_name\()_el\()\el 22*91f16700Schasinglulu .endm 23*91f16700Schasinglulu 24*91f16700Schasinglulu .macro tlbi_invalidate_all el 25*91f16700Schasinglulu .if \el == 1 26*91f16700Schasinglulu TLB_INVALIDATE(vmalle1) 27*91f16700Schasinglulu .elseif \el == 2 28*91f16700Schasinglulu TLB_INVALIDATE(alle2) 29*91f16700Schasinglulu .elseif \el == 3 30*91f16700Schasinglulu TLB_INVALIDATE(alle3) 31*91f16700Schasinglulu .else 32*91f16700Schasinglulu .error "EL must be 1, 2 or 3" 33*91f16700Schasinglulu .endif 34*91f16700Schasinglulu .endm 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* void enable_mmu_direct_el<x>(unsigned int flags) */ 37*91f16700Schasinglulu .macro define_mmu_enable_func el 38*91f16700Schasinglulu func enable_mmu_direct_\()el\el 39*91f16700Schasinglulu#if ENABLE_ASSERTIONS 40*91f16700Schasinglulu _mrs x1, sctlr, \el 41*91f16700Schasinglulu tst x1, #SCTLR_M_BIT 42*91f16700Schasinglulu ASM_ASSERT(eq) 43*91f16700Schasinglulu#endif 44*91f16700Schasinglulu /* Invalidate all TLB entries */ 45*91f16700Schasinglulu tlbi_invalidate_all \el 46*91f16700Schasinglulu 47*91f16700Schasinglulu mov x7, x0 48*91f16700Schasinglulu adrp x0, mmu_cfg_params 49*91f16700Schasinglulu add x0, x0, :lo12:mmu_cfg_params 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* MAIR */ 52*91f16700Schasinglulu ldr x1, [x0, #(MMU_CFG_MAIR << 3)] 53*91f16700Schasinglulu _msr mair, \el, x1 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* TCR */ 56*91f16700Schasinglulu ldr x2, [x0, #(MMU_CFG_TCR << 3)] 57*91f16700Schasinglulu _msr tcr, \el, x2 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* TTBR */ 60*91f16700Schasinglulu ldr x3, [x0, #(MMU_CFG_TTBR0 << 3)] 61*91f16700Schasinglulu _msr ttbr0, \el, x3 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* 64*91f16700Schasinglulu * Ensure all translation table writes have drained into memory, the TLB 65*91f16700Schasinglulu * invalidation is complete, and translation register writes are 66*91f16700Schasinglulu * committed before enabling the MMU 67*91f16700Schasinglulu */ 68*91f16700Schasinglulu dsb ish 69*91f16700Schasinglulu isb 70*91f16700Schasinglulu 71*91f16700Schasinglulu /* Set and clear required fields of SCTLR */ 72*91f16700Schasinglulu _mrs x4, sctlr, \el 73*91f16700Schasinglulu mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT 74*91f16700Schasinglulu orr x4, x4, x5 75*91f16700Schasinglulu 76*91f16700Schasinglulu /* Additionally, amend SCTLR fields based on flags */ 77*91f16700Schasinglulu bic x5, x4, #SCTLR_C_BIT 78*91f16700Schasinglulu tst x7, #DISABLE_DCACHE 79*91f16700Schasinglulu csel x4, x5, x4, ne 80*91f16700Schasinglulu 81*91f16700Schasinglulu _msr sctlr, \el, x4 82*91f16700Schasinglulu isb 83*91f16700Schasinglulu 84*91f16700Schasinglulu ret 85*91f16700Schasinglulu endfunc enable_mmu_direct_\()el\el 86*91f16700Schasinglulu .endm 87*91f16700Schasinglulu 88*91f16700Schasinglulu /* 89*91f16700Schasinglulu * Define MMU-enabling functions for EL1, EL2 and EL3: 90*91f16700Schasinglulu * 91*91f16700Schasinglulu * enable_mmu_direct_el1 92*91f16700Schasinglulu * enable_mmu_direct_el2 93*91f16700Schasinglulu * enable_mmu_direct_el3 94*91f16700Schasinglulu */ 95*91f16700Schasinglulu define_mmu_enable_func 1 96*91f16700Schasinglulu define_mmu_enable_func 2 97*91f16700Schasinglulu define_mmu_enable_func 3 98