1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <assert_macros.S> 9*91f16700Schasinglulu#include <lib/xlat_tables/xlat_tables_v2.h> 10*91f16700Schasinglulu#include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .global enable_mpu_direct_el2 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* void enable_mmu_direct_el2(unsigned int flags) */ 15*91f16700Schasinglulufunc enable_mpu_direct_el2 16*91f16700Schasinglulu#if ENABLE_ASSERTIONS 17*91f16700Schasinglulu mrs x1, sctlr_el2 18*91f16700Schasinglulu tst x1, #SCTLR_M_BIT 19*91f16700Schasinglulu ASM_ASSERT(eq) 20*91f16700Schasinglulu#endif 21*91f16700Schasinglulu mov x7, x0 22*91f16700Schasinglulu adrp x0, mmu_cfg_params 23*91f16700Schasinglulu add x0, x0, :lo12:mmu_cfg_params 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* (MAIRs are already set up) */ 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* TCR */ 28*91f16700Schasinglulu ldr x2, [x0, #(MMU_CFG_TCR << 3)] 29*91f16700Schasinglulu msr tcr_el2, x2 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* 32*91f16700Schasinglulu * Ensure all translation table writes have drained into memory, the TLB 33*91f16700Schasinglulu * invalidation is complete, and translation register writes are 34*91f16700Schasinglulu * committed before enabling the MMU 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu dsb ish 37*91f16700Schasinglulu isb 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* Set and clear required fields of SCTLR */ 40*91f16700Schasinglulu mrs x4, sctlr_el2 41*91f16700Schasinglulu mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT 42*91f16700Schasinglulu orr x4, x4, x5 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* Additionally, amend SCTLR fields based on flags */ 45*91f16700Schasinglulu bic x5, x4, #SCTLR_C_BIT 46*91f16700Schasinglulu tst x7, #DISABLE_DCACHE 47*91f16700Schasinglulu csel x4, x5, x4, ne 48*91f16700Schasinglulu 49*91f16700Schasinglulu msr sctlr_el2, x4 50*91f16700Schasinglulu isb 51*91f16700Schasinglulu 52*91f16700Schasinglulu ret 53*91f16700Schasingluluendfunc enable_mpu_direct_el2 54