1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu 9*91f16700Schasinglulu .globl spin_lock 10*91f16700Schasinglulu .globl spin_unlock 11*91f16700Schasinglulu 12*91f16700Schasinglulu#if ARM_ARCH_AT_LEAST(8, 0) 13*91f16700Schasinglulu/* 14*91f16700Schasinglulu * According to the ARMv8-A Architecture Reference Manual, "when the global 15*91f16700Schasinglulu * monitor for a PE changes from Exclusive Access state to Open Access state, 16*91f16700Schasinglulu * an event is generated.". This applies to both AArch32 and AArch64 modes of 17*91f16700Schasinglulu * ARMv8-A. As a result, no explicit SEV with unlock is required. 18*91f16700Schasinglulu */ 19*91f16700Schasinglulu#define COND_SEV() 20*91f16700Schasinglulu#else 21*91f16700Schasinglulu#define COND_SEV() sev 22*91f16700Schasinglulu#endif 23*91f16700Schasinglulu 24*91f16700Schasinglulufunc spin_lock 25*91f16700Schasinglulu mov r2, #1 26*91f16700Schasinglulu1: 27*91f16700Schasinglulu ldrex r1, [r0] 28*91f16700Schasinglulu cmp r1, #0 29*91f16700Schasinglulu wfene 30*91f16700Schasinglulu strexeq r1, r2, [r0] 31*91f16700Schasinglulu cmpeq r1, #0 32*91f16700Schasinglulu bne 1b 33*91f16700Schasinglulu dmb 34*91f16700Schasinglulu bx lr 35*91f16700Schasingluluendfunc spin_lock 36*91f16700Schasinglulu 37*91f16700Schasinglulu 38*91f16700Schasinglulufunc spin_unlock 39*91f16700Schasinglulu mov r1, #0 40*91f16700Schasinglulu stl r1, [r0] 41*91f16700Schasinglulu COND_SEV() 42*91f16700Schasinglulu bx lr 43*91f16700Schasingluluendfunc spin_unlock 44