1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <stdbool.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <arch.h> 10*91f16700Schasinglulu #include <arch_helpers.h> 11*91f16700Schasinglulu #include <lib/extensions/sys_reg_trace.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx) 14*91f16700Schasinglulu { 15*91f16700Schasinglulu /* 16*91f16700Schasinglulu * CPTR_EL3.TTA: Set to zero so that System register accesses to the 17*91f16700Schasinglulu * trace registers do not trap to EL3. 18*91f16700Schasinglulu */ 19*91f16700Schasinglulu uint64_t val = per_world_ctx->ctx_cptr_el3; 20*91f16700Schasinglulu val &= ~(TTA_BIT); 21*91f16700Schasinglulu per_world_ctx->ctx_cptr_el3 = val; 22*91f16700Schasinglulu } 23*91f16700Schasinglulu 24*91f16700Schasinglulu void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu /* 27*91f16700Schasinglulu * CPTR_EL3.TTA: Set to one so that System register accesses to the 28*91f16700Schasinglulu * trace registers trap to EL3, unless it is trapped by CPACR.TRCDIS, 29*91f16700Schasinglulu * CPACR_EL1.TTA, or CPTR_EL2.TTA 30*91f16700Schasinglulu */ 31*91f16700Schasinglulu uint64_t val = per_world_ctx->ctx_cptr_el3; 32*91f16700Schasinglulu val |= TTA_BIT; 33*91f16700Schasinglulu per_world_ctx->ctx_cptr_el3 = val; 34*91f16700Schasinglulu } 35*91f16700Schasinglulu 36*91f16700Schasinglulu void sys_reg_trace_init_el2_unused(void) 37*91f16700Schasinglulu { 38*91f16700Schasinglulu /* 39*91f16700Schasinglulu * CPTR_EL2.TTA: Set to zero so that Non-secure System register accesses 40*91f16700Schasinglulu * to the trace registers from both Execution states do not trap to 41*91f16700Schasinglulu * EL2. If PE trace unit System registers are not implemented then this 42*91f16700Schasinglulu * bit is reserved, and must be set to zero. 43*91f16700Schasinglulu */ 44*91f16700Schasinglulu write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TTA_BIT); 45*91f16700Schasinglulu } 46